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    Method of fabricating u-gate transistor
    3.
    发明专利
    Method of fabricating u-gate transistor 有权
    制造U型门极晶体管的方法

    公开(公告)号：JP2011181952A

    公开(公告)日：2011-09-15

    申请号：JP2011103293

    申请日：2011-05-02

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： DOYLE BRIAN ,  SINGH SURINDER ,  SHAH UDAY ,  BRASK JUSTIN ,  CHAU ROBERT

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/7853 ,  H01L29/66795

    Abstract: PROBLEM TO BE SOLVED: To provide a non-planar semiconductor transistor structure which improves the short channel performance, and to provide a manufacturing method for the structure.
    SOLUTION: A U-shaped fin 305 is formed on an insulating layer 301 which resides on a substrate 360; a gate dielectric layer 362 and a gate electrode 363 are formed on one part of the fin; and a source region 403 and a drain region 404 are formed on both sides of the U-shaped fin 305. The gate electrode 363, together with a gate dielectric layer 362, covers a top surface 306 of one part of the U-shaped fin 305, and two sidewalls 307 which reside the opposite position, and a bottom 320 of one part of a recess 319, which resides in the U-shaped fin 305 and opposing two sidewalls 364, and substantially increases the width of the channel region that allows flow of a current. The current/voltage characteristics of a U-shaped transistor structure is controlled by the performance of a corner part of a device, over the entire gate voltage range, and thereby the short-channel effect is suppressed minimally; and a current under a threshold and a drive current are optimized.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种提高短通道性能的非平面半导体晶体管结构，并提供该结构的制造方法。 解决方案：U形翅片305形成在驻留在基板360上的绝缘层301上; 栅极电介质层362和栅电极363形成在翅片的一部分上; 并且源极区域403和漏极区域404形成在U形翅片305的两侧。栅极电极363与栅极电介质层362一起覆盖U形鳍片的一部分的顶表面306 305和位于相对位置的两个侧壁307和位于U形翅片305中并且相对的两个侧壁364的凹部319的一部分的底部320，并且基本上增加了允许的通道区域的宽度 电流流动。 在整个栅极电压范围内，U形晶体管结构的电流/电压特性由器件的角部的性能控制，从而最小限度地抑制了短沟道效应。 并且优化了阈值以下的电流和驱动电流。 版权所有（C）2011，JPO＆INPIT

    Method of manufacturing u-gate transistor
    4.
    发明专利
    Method of manufacturing u-gate transistor 有权
    制造U型栅极晶体管的方法

    公开(公告)号：JP2011176353A

    公开(公告)日：2011-09-08

    申请号：JP2011103294

    申请日：2011-05-02

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： DOYLE BRIAN ,  SINGH SURINDER ,  SHAH UDAY ,  BRASK JUSTIN ,  CHAU ROBERT

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/7853 ,  H01L29/66795

    Abstract: PROBLEM TO BE SOLVED: To provide a U-gate transistor that prevents a short channel effect which becomes a main restriction factor when an MOS transistor is miniaturized.
    SOLUTION: A process for manufacturing of a non-planar multi-corner transistor structure is constituted as follows. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin, exposing a top surface of the mask, wherein a protection layer is deposited between the fin and the second insulating layer. Next, the mask is removed and a spacer is formed in the fin adjacent to the protection layer. A recess having a bottom and opposing sidewalls is formed in the fin. A gate dielectric layer 362 and a gate electrode 363 are formed on the top surface and the opposing sidewalls of the fin 305 and on the bottom and the opposing sidewalls of the recess in the fin. A source region 403 and a drain region 404 are formed in the fin at the opposite sides of the gate electrode 363.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种防止在MOS晶体管小型化时成为主要限制因素的短沟道效应的U型栅极晶体管。 解决方案：制造非平面多角晶体管结构的方法如下构成。 在第一绝缘层上形成具有在鳍的顶表面上的掩模的半导体材料的鳍。 在翅片上形成第二绝缘层，露出掩模的顶表面，其中保护层沉积在散热片和第二绝缘层之间。 接下来，去除掩模并且在与保护层相邻的翅片中形成间隔物。 在翅片中形成具有底部和相对侧壁的凹部。 栅极电介质层362和栅电极363形成在翅片305的顶表面和相对的侧壁上，并且在鳍的底部和相对的侧壁上形成。 源极区域403和漏极区域404形成在栅极电极363的相对侧的鳍中。版权所有：（C）2011，JPO＆INPIT

    METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS
    8.
    发明申请
    METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS 审中-公开
    制造不同高度的相邻硅片的方法

    公开(公告)号：WO2009032576A3

    公开(公告)日：2009-05-07

    申请号：PCT/US2008074161

    申请日：2008-08-25

    Applicant: INTEL CORP ,  DOYLE BRIAN S ,  JIN BEEN-YIH ,  SHAH UDAY

    Inventor： DOYLE BRIAN S ,  JIN BEEN-YIH ,  SHAH UDAY

    IPC: H01L21/8244 ,  H01L27/11

    CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66795

    Abstract: A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin.

    Abstract translation: 制造具有不同高度的相邻硅鳍的方法包括：提供其上沉积有隔离层的硅衬底;图案化隔离层以形成第一和第二隔离结构;图案化硅衬底以在第一隔离结构下形成第一硅鳍;以及 在所述第二隔离结构下方的第二硅鳍状物，在所述衬底上沉积绝缘层，平坦化所述绝缘层以暴露所述第一和第二隔离结构的顶表面，沉积并图案化掩模层以掩蔽所述第一隔离结构而不是所述第二 施加湿蚀刻以去除第二隔离结构并暴露第二硅鳍;在第二硅鳍上外延沉积硅层;以及使绝缘层凹陷以暴露第一硅鳍的至少一部分，并且至少 第二硅鳍的一部分。

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