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    Creating an isolated execution environment in a co-designed processor
    1.
    发明专利
    Creating an isolated execution environment in a co-designed processor 未知

    公开(公告)号：GB2514221A

    公开(公告)日：2014-11-19

    申请号：GB201404228

    申请日：2014-03-11

    Applicant: INTEL CORP

    Inventor： YAMADA KOICHI ,  SHANMUGAVELAYUTHAM PALANIVEL RAJAN ,  RODGERS SCOTT D ,  HUNTLEY BARRY E ,  BEANEY JAMES D JR ,  TAMIR BOAZ

    IPC: G06F9/455

    Abstract: A co-designed processor 605, such as a heterogeneous multi-core processor, includes, isolated from a software stack and transparent thereto by way of means such as concealed memory 640, a binary translation (BT) engine 645 having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache 648. The binary translated code may include a routine to emulate an instruction not provided in the target ISA such as an instruction with a vector operand wherein a width of a datapath of the target core is less than a width of the vector operand. The heterogeneous multi-core processor may include a first and second core for executing instructions of a first ISA and a second ISA respectively wherein the second ISA may be different to the first ISA or a subset thereof. The second core may have lower power consumption than the first core and the binary translation may be from the first ISA to the second ISA.

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