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    LATENCY NORMALIZATION BY BALANCING EARLY AND LATE CLOCKS
    1.
    发明申请
    LATENCY NORMALIZATION BY BALANCING EARLY AND LATE CLOCKS 审中-公开
    通过平衡早期和时间来暂时标准化

    公开(公告)号：WO2006036569A3

    公开(公告)日：2006-06-08

    申请号：PCT/US2005032927

    申请日：2005-09-13

    Applicant: INTEL CORP ,  TO HING ,  SALMON JOE ,  RASHID MAMUN

    Inventor： TO HING ,  SALMON JOE ,  RASHID MAMUN

    IPC: G06F1/10

    CPC classification number: G06F1/10

    Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

    Abstract translation: 公开了一种方法，装置和系统。 在一个实施例中，该方法包括将早期时钟信号和后期时钟信号输入到存储器件，并通过对早期时钟信号和后期时钟信号进行平均来产生存储器件的平均时钟信号。

    3.
    发明专利
    未知

    公开(公告)号：DE112005002333T5

    公开(公告)日：2007-08-16

    申请号：DE112005002333

    申请日：2005-09-13

    Applicant: INTEL CORP

    Inventor： TO HING ,  SALMON JOE ,  RASHID MAMUN

    IPC: G06F1/10

    Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

    4.
    发明专利
    未知

    公开(公告)号：AT425498T

    公开(公告)日：2009-03-15

    申请号：AT03761910

    申请日：2003-05-22

    Applicant: INTEL CORP

    Inventor： SALMON JOSEPH ,  TO HING

    IPC: G06F13/42 ,  G06F11/00 ,  G11C8/00 ,  G11C29/50 ,  H04J3/06 ,  H04L1/24

    Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

    Reaktionszeitnormierung durch ausgleichen voreilender und nacheilender Takte
    6.
    发明专利
    Reaktionszeitnormierung durch ausgleichen voreilender und nacheilender Takte 未知

    公开(公告)号：DE112005002333B4

    公开(公告)日：2015-04-09

    申请号：DE112005002333

    申请日：2005-09-13

    Applicant: INTEL CORP

    Inventor： TO HING ,  SALMON JOE ,  RASHID MAMUN

    IPC: G11C7/22 ,  G06F1/10

    Abstract: Vorrichtung, umfassend: eine von einem Memory Controller Hub (MCH) (200) ausgehende Taktsignalleiterbahn (202); und eine Speichervorrichtung (214, 218, 222), welche sich auf einem Speichermodul (204) befindet, wobei das Speichermodul (204) von dem MCH (200) getrennt ist, wobei die Speichervorrichtung (214, 218, 222) betriebsfähig ist, um: ein voreilendes Taktsignal (212) von der Taktsignalleiterbahn (202) und ein nacheilendes Taktsignal (228) von der Taktsignalleiterbahn zu empfangen; eine Taktsequenz des voreilenden Signals zu bestimmen, eine Taktsequenz des nacheilenden Signals zu bestimmen, und ein gemitteltes Taktsignal zu erzeugen, das eine Taktsequenz aufweist, die in der Mitte zwischen der Taktsequenz des voreilenden Signals und der Taktsequenz des nacheilenden Signals liegt; und einen auf dem Speichermodul (204) befindlichen Terminierungswiderstand (236) an dem Ende der Taktsignalleiterbahn (202), um das Taktsignal zu terminieren, nachdem die Speichervorrichtung (214, 218, 222) sowohl das voreilende als auch das nacheilende Taktsignal (212, 228) empfangen hat.

    8.
    发明专利
    未知

    公开(公告)号：DE60326584D1

    公开(公告)日：2009-04-23

    申请号：DE60326584

    申请日：2003-05-22

    Applicant: INTEL CORP

    Inventor： SALMON JOSEPH ,  TO HING

    IPC: G06F13/42 ,  G06F11/00 ,  G11C8/00 ,  G11C29/50 ,  H04J3/06 ,  H04L1/24

    Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

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