公开(公告)号：WO2023048798A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/037467

申请日：2022-07-18

Applicant: INTEL CORPORATION

Inventor： COLLINS, Andrew ,  PIETAMBARAM, Srinivas, V. ,  IBRAHIM, Tarek, A. ,  GANESAN, Sanka ,  VISWANATH, Ram, S.

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/15

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to glass core-based substrates with an asymmetric number of front and back-side copper layers. In embodiments, the front and/or backside copper layers may be referred to as stack ups or as buildup layers on the glass core substrate. Embodiments may allow lower overall substrate layer counts by allowing for more front side layers where the signal routing may typically be highest, without requiring a matching, or symmetric, number of backside copper layers. Other embodiments may be described and/or claimed.

公开(公告)号：WO2023048796A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/037331

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： COLLINS, Andrew ,  PIETAMBARAM, Srinivas, V. ,  GANESAN, Sanka ,  IBRAHIM, Tarek, A. ,  MORTENSEN, Russell

IPC: H01L25/065 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to packages that include one or more dies that are coupled with one or more glass layers. These glass layers may be within an interposer or a patch to which the one or more dies are attached. In addition, these glass layers may be used to facilitate pitch translation between the one or more dies proximate to a first side of the glass layer and a substrate proximate to a second side of the glass layer opposite the first side, to which the one or more dies are electrically coupled. Other embodiments may be described and/or claimed.

公开(公告)号：WO2023043529A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/037181

申请日：2022-07-14

Applicant: INTEL CORPORATION

Inventor： COLLINS, Andrew ,  PIETAMBARAM, Srinivas V. ,  XIE, Jianyong ,  VALAVALA, Krishna Vasanth

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.

公开(公告)号：WO2019190690A1

公开(公告)日：2019-10-03

申请号：PCT/US2019/020020

申请日：2019-02-28

Applicant: INTEL CORPORATION

Inventor： COLLINS, Andrew ,  MALLIK, Debendra ,  MANUSHAROW, Mathew J. ,  XIE, Jianyong

IPC: H01L23/528 ,  H01L25/065 ,  H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

公开(公告)号：EP4156255A1

公开(公告)日：2023-03-29

申请号：EP22191777.6

申请日：2022-08-23

Applicant: INTEL Corporation

Inventor： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  COLLINS, Andrew

IPC: H01L23/498 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

公开(公告)号：EP4203009A1

公开(公告)日：2023-06-28

申请号：EP22206289.5

申请日：2022-11-09

Applicant: INTEL Corporation

Inventor： ALEKSOV, Aleksandar ,  KAMGAING, Telesphor ,  DOGIAMIS, Georgios ,  PRABHU GAUNKAR, Neelam ,  STRONG, Veronica ,  RAWLINGS, Brandon ,  COLLINS, Andrew ,  SAIN, Arghya ,  PANDI, Sivaseetharaman

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.

公开(公告)号：EP4210097A1

公开(公告)日：2023-07-12

申请号：EP22205731.7

申请日：2022-11-07

Applicant: INTEL Corporation

Inventor： SAIN, Arghya ,  COLLINS, Andrew ,  PANDI, Sivaseetharaman ,  XIE, Jianyong ,  KAMGAING, Telesphor

IPC: H01L23/15 ,  H01L23/498

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.

公开(公告)号：EP4199070A1

公开(公告)日：2023-06-21

申请号：EP22213185.6

申请日：2022-12-13

Applicant: INTEL Corporation

Inventor： PANDI, Sivaseetharaman ,  COLLINS, Andrew ,  SAIN, Arghya ,  KAMGAING, Telesphor

IPC: H01L23/15 ,  H01L23/498 ,  H01L23/64

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass, and a first via through the core. In an embodiment, a first fin extends out laterally from the first via. In an embodiment, the electronic package further comprises a second via through the core, and a second fin extending out laterally from the second via. In an embodiment, a face of the first fin overlaps a face of the second fin.

公开(公告)号：EP3506350A1

公开(公告)日：2019-07-03

申请号：EP18208998.7

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： COLLINS, Andrew ,  PENMECHA, Bharat P. ,  SWAMINATHAN, Rajasekaran ,  VISWANATH, Ram

IPC: H01L23/538 ,  H01L23/498

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：EP4406021A1

公开(公告)日：2024-07-31

申请号：EP22873348.1

申请日：2022-07-15

Applicant: Intel Corporation

Inventor： COLLINS, Andrew ,  PIETAMBARAM, Srinivas, V. ,  GANESAN, Sanka ,  IBRAHIM, Tarek, A. ,  MORTENSEN, Russell

IPC: H01L25/065 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L23/15 ,  H01L23/5384 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/0655