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    DIELECTRIC-FILLED TRENCH ISOLATION OF VIAS
    1.
    发明申请
    DIELECTRIC-FILLED TRENCH ISOLATION OF VIAS 审中-公开

    公开(公告)号：WO2019190562A1

    公开(公告)日：2019-10-03

    申请号：PCT/US2018/025519

    申请日：2018-03-30

    Applicant: INTEL CORPORATION

    Inventor： AYGUN, Kemal ,  QIAN, Zhiguo ,  XIE, Jianyong

    IPC: H01L23/48 ,  H01L23/13 ,  H01L23/498

    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

    THICK AND THIN TRACES IN A BRIDGE WITH A GLASS CORE
    3.
    发明申请
    THICK AND THIN TRACES IN A BRIDGE WITH A GLASS CORE 审中-公开

    公开(公告)号：WO2023043529A1

    公开(公告)日：2023-03-23

    申请号：PCT/US2022/037181

    申请日：2022-07-14

    Applicant: INTEL CORPORATION

    Inventor： COLLINS, Andrew ,  PIETAMBARAM, Srinivas V. ,  XIE, Jianyong ,  VALAVALA, Krishna Vasanth

    IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.

    SEMICONDUCTOR PACKAGE WITH THROUGH BRIDGE DIE CONNECTIONS
    5.
    发明申请
    SEMICONDUCTOR PACKAGE WITH THROUGH BRIDGE DIE CONNECTIONS 审中-公开
    半导体封装通过桥接模具连接

    公开(公告)号：WO2017111957A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2015/067447

    申请日：2015-12-22

    Applicant: INTEL CORPORATION

    Inventor： QIAN, Zhiguo ,  XIE, Jianyong ,  AYGUN, Kemal

    IPC: H01L25/065 ,  H01L25/07 ,  H01L23/48

    CPC classification number: H01L24/20 ,  H01L25/065 ,  H01L25/07 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014

    Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

    Abstract translation: 公开了具有穿通桥芯片连接的半导体封装及其制造方法。 半导体封装可以容纳一个或多个电子组件作为封装（SiP）实现中的系统。 诸如嵌入式多芯片互连桥（EMIB）之类的桥接管芯可嵌入半导体封装的一个或多个构建层内。 桥接管芯可以具有导电块，其可以在背侧电连接到电源平面并且用于经由形成在桥接管芯的顶侧上的互连而将电力递送到附接到半导体封装的一个或多个管芯，电桥 到桥模的大部分。 与在桥芯片周围路由功率相比，可以实现通过桥芯片传输功率的更直接路径。

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