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    LOW POWER mmWAVE RECEIVER ARCHITECTURE WITH SPATIAL COMPRESSION INTERFACE
    2.
    发明申请
    LOW POWER mmWAVE RECEIVER ARCHITECTURE WITH SPATIAL COMPRESSION INTERFACE 审中-公开

    公开(公告)号：WO2019135733A1

    公开(公告)日：2019-07-11

    申请号：PCT/US2018/012066

    申请日：2018-01-02

    Applicant: INTEL CORPORATION

    Inventor： ORHAN, Oner ,  NIKOPOUR, Hosein ,  SAGAZIO, Peter ,  SHEIKH, Farhana ,  NAM, Junyoung ,  TALWAR, Shilpa

    IPC: H04B7/0413 ,  H04L29/06

    Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.

    PHASE MODULATION SYSTEMS AND METHODS
    3.
    发明申请
    PHASE MODULATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：WO2020009735A1

    公开(公告)日：2020-01-09

    申请号：PCT/US2019/026977

    申请日：2019-04-11

    Applicant: INTEL CORPORATION

    Inventor： AGRAWAL, Abhishek ,  PELLERANO, Stefano ,  SAGAZIO, Peter ,  WANG, Yanjie

    IPC: G11C7/22 ,  G11C11/4076 ,  H04L7/033 ,  G06F1/04

    Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

    CLOSED-LOOP BAUD RATE CARRIER AND CARRIER FREQUENCY TUNING FOR WIRELESS CHIP-TO-CHIP INTERFACE
    5.
    发明公开
    CLOSED-LOOP BAUD RATE CARRIER AND CARRIER FREQUENCY TUNING FOR WIRELESS CHIP-TO-CHIP INTERFACE 审中-公开

    公开(公告)号：EP4016852A1

    公开(公告)日：2022-06-22

    申请号：EP21194568.8

    申请日：2021-09-02

    Applicant: INTEL Corporation

    Inventor： SAGAZIO, Peter ,  LEE, Chun C. ,  PELLERANO, Stefano ,  HULL, Christopher D.

    IPC: H04B1/10

    Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.

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