公开(公告)号：WO2023048869A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/041123

申请日：2022-08-22

Applicant: INTEL CORPORATION

Inventor： LI, Xiaoqian ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PIETAMBARAM, Srinivas

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/18 ,  G02B6/122 ,  H01S5/0239 ,  H01L23/31 ,  H01L25/00 ,  G02B6/12

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an optical component optically coupled to the active surface of the PIC and extending at least partially through the first layer; and an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material, wherein the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active side of the PIC.

公开(公告)号：WO2017105772A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/062825

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： KARHADE, Omkar ,  DESHPANDE, Nitin ,  ZIADEH, Bassam M. ,  TOMITA, Yoshihiro

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

Abstract translation: 包括衬底的集成电路组件; 在基板上形成的部件; 第一模具，所述第一模具安装在所述构件中的开口内的所述基板上，使得在所述第一模具与所述构件之间存在空间，并且所述构件围绕所述第一模具，并且其中所述第一模具不延伸到所述构件的上表面之上; 在所述第一模具和所述衬底之间的底部填充物，其中所述底部填充物至少部分地填充所述模具和部件之间的空间; 以及安装到第一模具和构件的第二模具，其中第二模具在开口的所有侧上安装到构件。

公开(公告)号：WO2022139827A1

公开(公告)日：2022-06-30

申请号：PCT/US2020/066747

申请日：2020-12-23

Applicant: INTEL CORPORATION

Inventor： ACIKALIN, Tolga ,  YANG, Tae, Young ,  CHOUDHURY, Debabani ,  YAMADA, Shuhei ,  DOOSTNEJAD, Roya ,  NIKOPOUR, Hosein ,  KIPNIS, Issy ,  ORHAN, Oner ,  RAHMAN, Mehnaz ,  FOUST, Kenneth P. ,  HULL, Christopher, D. ,  KAMGAING, Telesphor ,  KARHADE, Omkar ,  PELLERANO, Stefano ,  SAGAZIO, Peter ,  VADLAMANI, Sai

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532 ,  H01L23/66 ,  H01L23/498 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/50

Abstract: Various devices, systems, and/or methods perform wireless chip to chip high speed data transmission. Strategies for such transmission include use of improved microbump antennas, wireless chip to chip interconnects, precoding and decoding strategies, channel design to achieve spatial multiplexing gain in line of sight transmissions, open cavity chip design for improved transmission, and/or mixed signal channel equalization.

公开(公告)号：WO2017111950A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/067418

申请日：2015-12-22

Applicant: INTEL CORPORATION ,  DESHPANDE, Nitin ,  LIFF, Shawna M. ,  EITAN, Amram

Inventor： DESHPANDE, Nitin ,  LIFF, Shawna M. ,  EITAN, Amram ,  LI, Eric ,  KARHADE, Omkar ,  GOSSELIN, Timothy A.

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L23/13 ,  H01L23/36 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

Abstract translation: 包括具有上表面的基板和包括上表面的桥的电子组件。 桥位于基板上表面的空腔内。 第一电子元件连接到电桥的上表面和基板的上表面，第二电子元件连接到电桥的上表面和基板的上表面，其中桥电连接第一电子元件 组件连接到第二电子组件。

公开(公告)号：WO2017105661A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/060316

申请日：2016-11-03

Applicant: INTEL CORPORATION ,  LAMBERT, William J. ,  O'BRIEN, Kevin

Inventor： LAMBERT, William J. ,  O'BRIEN, Kevin ,  KARHADE, Omkar

IPC: H01F27/28 ,  H01F17/00

CPC classification number: H01F27/2823 ,  C23C14/35 ,  C23C14/505 ,  C23C28/42 ,  C23C28/44 ,  H01F17/04 ,  H01F27/32 ,  H01F41/12

Abstract: Apparatus and methods are provided for a wire based inductor component. In an example, an inductor apparatus can include a wire and a plurality of individual layers of magnetic material surrounding the wire.

Abstract translation: 提供了用于基于电线的电感器组件的设备和方法。 在一个示例中，电感器装置可以包括导线和围绕导线的多个单独的磁性材料层。

公开(公告)号：WO2022139908A1

公开(公告)日：2022-06-30

申请号：PCT/US2021/051137

申请日：2021-09-20

Applicant: INTEL CORPORATION

Inventor： ZHANG, Zhichao ,  AYGÜN, Kemal ,  POTHUKUCHI, Suresh V. ,  LI, Xiaoqian ,  KARHADE, Omkar

IPC: H01L25/16 ,  H01L23/36 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：WO2022139905A1

公开(公告)日：2022-06-30

申请号：PCT/US2021/050895

申请日：2021-09-17

Applicant: INTEL CORPORATION

Inventor： LI, Xiaoqian ,  DESHPANDE, Nitin ,  KARHADE, Omkar ,  MAHAJAN, Ravindranath V.

IPC: H01L25/16 ,  H01L23/36 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

公开(公告)号：WO2022108647A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/049666

申请日：2021-09-09

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC: G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：WO2019133008A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069138

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  MALLIK, Debendra ,  SANKMAN, Robert L. ,  NICKERSON, Robert ,  MODI, Mitul ,  GANESAN, Sanka ,  SWAMINATHAN, Rajasekaran ,  KARHADE, Omkar ,  LIFF, Shawna M. ,  ALUR, Amruthavalli ,  CHAVALI, Sri Chaitra J.

Inventor： MALLIK, Debendra ,  SANKMAN, Robert L. ,  NICKERSON, Robert ,  MODI, Mitul ,  GANESAN, Sanka ,  SWAMINATHAN, Rajasekaran ,  KARHADE, Omkar ,  LIFF, Shawna M. ,  ALUR, Amruthavalli ,  CHAVALI, Sri Chaitra J.

IPC: H01L25/07 ,  H01L23/538 ,  H01L23/498 ,  H01L23/28 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 µm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：WO2017105690A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/061471

申请日：2016-11-11

Applicant: INTEL CORPORATION

Inventor： KARHADE, Omkar ,  DHANE, Kedar

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/16 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic package that includes a substrate; a die attached to the substrate; an underfill positioned between the die and the substrate due to capillary action; a first support adjacent to the die and attached to the substrate; and a second support mounted on the first support, wherein the second support is closer to the die than the first support, wherein first support surrounds the die and the second support surrounds the die, and wherein the second support is a different material than the first support. The die may be flip chip bonded to the substrate and the underfill may secure the die to the substrate. The first support may be attached to the substrate using an adhesive and the second support may be attached to the first support using an adhesive.

Abstract translation: 包括衬底的电子封装; 附着到衬底的管芯; 由于毛细管作用而位于管芯和基底之间的底部填充物; 与管芯相邻并附着到衬底的第一支撑件; 以及安装在所述第一支撑件上的第二支撑件，其中所述第二支撑件比所述第一支撑件更靠近所述裸片，其中第一支撑件围绕所述裸片并且所述第二支撑件围绕所述裸片，并且其中所述第二支撑件是与所述第一支撑件不同的材料 支持。 管芯可以倒装芯片结合到衬底并且底部填充物可以将管芯固定到衬底。 可以使用粘合剂将第一支撑物附着到基底上，并且可以使用粘合剂将第二支撑物附着到第一支撑物上。