公开(公告)号：US20030040185A1

公开(公告)日：2003-02-27

申请号：US09938042

申请日：2001-08-23

Applicant: Institute of Microelectronics

Inventor： Cai Jun ,  Ren Chang Hong ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian ,  Yung Chii Liang

IPC: H01L021/302 ,  H01L021/461 ,  H01L021/311

CPC classification number: H01L29/7835 ,  H01L21/76208 ,  H01L21/7624 ,  H01L29/0653 ,  H01L29/66659

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep tenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device

Abstract translation: 描述了用于部分SOI结构的掩埋氧化物层的制造方法。 该过程开始于将深层刻蚀成硅体。 对于表面下方的预选深度，沟槽的内壁被保护，然后进行所述壁的氧化，直到在沟槽内部以及沟槽之间的材料发生夹断。 结果是连续的氧化层，其尺寸和形状由沟槽的数量和位置决定。 本方法还应用于部分SOI RFLDMOS结构的制造以及所得到的器件的性能数据

公开(公告)号：US20030209076A1

公开(公告)日：2003-11-13

申请号：US10409421

申请日：2003-04-08

Applicant: Institute of microelectronics

Inventor： Yubo Miao ,  Ranganathan Nagarajan ,  Uppili Sridhar ,  Rakesh Kumar ,  Qinxin Zhang

IPC: G01P015/125

CPC classification number: G01P15/125 ,  B81B3/0051 ,  B81B2201/0235 ,  B81B2203/053 ,  G01P15/0802 ,  G01P2015/0814 ,  Y10T29/49005

Abstract: An accelerometer design is described. It operates by measuring a change in capacitance when one plate is fixed and one is mobile (free to accelerate). Unlike prior art designs where such changes are caused by variations in the plate separation distance, in the design of the present invention the plate separation distance is fixed, it being the effective plate area that changes with acceleration. A key feature is that the basic unit is a pair of capacitors. The fixed plates in each case are at the same relative height but the mobile plates are offset relative to the fixed plates, one mobile plate somewhat higher than its fixed plate with the other mobile plate being somewhat lower. Then, when the mobile plates move (in the same direction), one capacitor increases in value while the other decreases by the same amount. This differential design renders the device insensitive to sources of systematic error such as temperature changes. A process for manufacturing the design is described.

Abstract translation: 描述加速度计设计。 它通过测量一个板固定并且一个是移动的（自由加速）时的电容变化来操作。 不同于现有技术设计，其中这种变化是由板间隔距离的变化引起的，在本发明的设计中，板间隔距离是固定的，它是加速度变化的有效板面积。 一个关键的特征是基本单元是一对电容器。 每种情况下的固定板具有相同的相对高度，但是移动板相对于固定板偏移，一个移动板稍微高于其固定板，另一个移动板稍低。 然后，当移动板移动（沿相同方向）时，一个电容器的值增加，而另一个电容器减少相同的量。 该差分设计使设备对温度变化等系统误差源不敏感。 描述了用于制造设计的过程。

公开(公告)号：US20030219683A1

公开(公告)日：2003-11-27

申请号：US10154280

申请日：2002-05-23

Applicant: Institute of Microelectronics.

Inventor： Ranganathan Nagarajan ,  Shajan Mathew ,  Lakshmi Kanta Bera

IPC: G03F007/16 ,  G03F007/20 ,  G03F007/40 ,  G03F007/36 ,  G21K005/00

CPC classification number: G03F7/40 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (

Abstract translation: 描述了在半导体器件和MEMS器件的集成电路的制造期间修整光致抗蚀剂图案的过程。 使用低温（<20℃），高密度氧和氩等离子体和强烈的紫外线辐射的组合来同时修整和硬化ICP腔中的光致抗蚀剂线宽。 作为替代，在ICP等离子体蚀刻之前，可以在泛光曝光工具中执行UV硬化步骤。 另一个选择是首先进行氩等离子体处理以使抗蚀剂硬化，然后在第二步骤中施加氧等离子体来修整光致抗蚀剂。 以可控的方式降低垂直和水平蚀刻速率，这对于在小于100nm的MOS晶体管中产生栅极长度是有用的。 该方法还可以用于可控地增加光致抗蚀剂特征中的空间宽度。

公开(公告)号：US20030218227A1

公开(公告)日：2003-11-27

申请号：US10154279

申请日：2002-05-23

Applicant: Institute of Microelectronics.

Inventor： Janak Singh ,  Uppili Sridhar ,  Ranganathan Nagarajan ,  Quanbo Zou

IPC: H01L031/0232

CPC classification number: B81C1/00142 ,  B81B2201/042 ,  G02B26/0841

Abstract: Design of a micro-mirror switching device and its fabrication in single crystal silicon are described. The device is composed of three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Abstract translation: 描述了微镜开关器件的设计及其在单晶硅中的制造。 该装置由三个主要元件组成：具有金属镜的硅镜板，二次致动器和用于将镜板与致动器集成的铰链/弹簧机构。 p-n结首先在p型硅上形成。 然后在n硅中蚀刻沟槽以限定器件元件边界并填充二氧化硅。 沉积和图案化三层牺牲氧化物和两个结构多晶硅层以形成器件元件。 由氢氧化钾中的背面电化学蚀刻，从底部暴露氧化物填充的沟槽的反应离子蚀刻和硅沟槽中的牺牲氧化物层和氧化物的氢氟酸蚀刻组成的新型释放过程形成硅块; 牺牲未附着于结构多晶硅的那些，并且将附着的那些留在适当位置以将开关元件元件保持在一起。

公开(公告)号：US20020166838A1

公开(公告)日：2002-11-14

申请号：US09900293

申请日：2001-07-06

Applicant: Institute of Microelectronics

Inventor： Ranganathan Nagarajan

IPC: H01L021/302

CPC classification number: H01L21/3086 ,  B81B2203/033 ,  B81B2203/0384 ,  B81C1/00103 ,  G01P15/0802

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract translation: 用于蚀刻具有高度可控壁分布的材料层中的锥形沟槽的方法和装置。 材料层具有邻近其表面的掩模，该掩模具有限定在其上将形成沟槽的材料层上的位置的开口。 然后以交替的方式执行垂直蚀刻工艺步骤和开放扩大工艺步骤，直到沟槽已经被蚀刻到期望的深度。 该方法允许以高度可控的方式在硅衬底或其它材料层中形成高达80-100μm或更大的非常深的锥形沟槽。 该方法可以并入用于制造包括MEMS器件和诸如LDMOS和VDMOS器件的高功率RF器件的许多器件的工艺中。