公开(公告)号：US20250112163A1

公开(公告)日：2025-04-03

申请号：US18375203

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Pratyasha Mohapatra ,  Srinivas Pietambaram ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Yosef Kornbluth ,  Kuang Liu ,  Astitva Tripathi ,  Yuqin Li ,  Rengarajan Shanmugam ,  Xing Sun ,  Brian Balch ,  Darko Grujicic ,  Jieying Kong ,  Nicholas Haehn ,  Jacob Vehonsky ,  Mitchell Page ,  Vincent Obiozo Eze ,  Daniel Wandera ,  Sameer Paital ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L25/065

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.

公开(公告)号：US20250112175A1

公开(公告)日：2025-04-03

申请号：US18477638

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jesse C. Jones ,  Yosef Kornbluth ,  Mitchell Page ,  Soham Agarwal ,  Fanyi Zhu ,  Shuren Qu ,  Hanyu Song ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Bai Nie ,  Nicholas Haehn ,  Astitva Tripathi ,  Mohamed R. Saber ,  Sheng Li ,  Pratyush Mishra ,  Benjamin T. Duong ,  Kari Hernandez ,  Praveen Sreeramagiri ,  Yi Li ,  Ibrahim El Khatib ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Haobo Chen ,  Robin Shea McRee ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L25/065

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

Abstract: Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.