公开(公告)号：US20210035950A1

公开(公告)日：2021-02-04

申请号：US17076433

申请日：2020-10-21

Applicant: Intel IP Corporation

Inventor： Richard PATTEN

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00

Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.

公开(公告)号：US20190109114A1

公开(公告)日：2019-04-11

申请号：US15743142

申请日：2015-08-28

Applicant: Intel IP Corporation

Inventor： Richard PATTEN

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.

公开(公告)号：US20180358317A1

公开(公告)日：2018-12-13

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/552 ,  H01L23/433 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20200219844A1

公开(公告)日：2020-07-09

申请号：US16818961

申请日：2020-03-13

Applicant: Intel IP Corporation

Inventor： Richard PATTEN

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.

公开(公告)号：US20200273832A1

公开(公告)日：2020-08-27

申请号：US16871325

申请日：2020-05-11

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC: H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L23/552 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20200176436A1

公开(公告)日：2020-06-04

申请号：US15776378

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Richard PATTEN ,  Georg SEIDEMANN ,  Christian GEISSLER

IPC: H01L25/00 ,  H01L25/065

Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

公开(公告)号：US20180331070A1

公开(公告)日：2018-11-15

申请号：US15774906

申请日：2015-12-26

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.