公开(公告)号：US20170284636A1

公开(公告)日：2017-10-05

申请号：US15087477

申请日：2016-03-31

Applicant: Intel IP Corporation

Inventor： Marc Stephan Dittes ,  Sven Albers ,  Christian Georg Geissler ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Thomas Wagner ,  Richard Patten

IPC: F21V11/00 ,  F21V23/00 ,  H01L33/58 ,  H01L33/54 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/73257 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

公开(公告)号：US10672731B2

公开(公告)日：2020-06-02

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20190312016A1

公开(公告)日：2019-10-10

申请号：US15945648

申请日：2018-04-04

Applicant: Intel IP Corporation

Inventor： David O'Sullivan ,  Georg Seidemann ,  Richard Patten ,  Bernd Waidhas

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20190121041A1

公开(公告)日：2019-04-25

申请号：US16090024

申请日：2016-03-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Marc Dittes ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Thomas Wagner ,  Richard Patten

IPC: G02B6/42 ,  H01L23/00

Abstract: Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.

公开(公告)号：US10854590B2

公开(公告)日：2020-12-01

申请号：US15776378

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Richard Patten ,  Georg Seidemann ,  Christian Geissler

IPC: H01L23/02 ,  H01L25/00 ,  H01L25/065 ,  H05K1/11

Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

公开(公告)号：US10816742B2

公开(公告)日：2020-10-27

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/30 ,  G02B6/12 ,  G02B6/43

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10411000B2

公开(公告)日：2019-09-10

申请号：US15087477

申请日：2016-03-31

Applicant: Intel IP Corporation

Inventor： Marc Stephan Dittes ,  Sven Albers ,  Christian Georg Geissler ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Thomas Wagner ,  Richard Patten

IPC: F21V15/00 ,  H01L25/16 ,  H01L23/31

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

公开(公告)号：US20170178999A1

公开(公告)日：2017-06-22

申请号：US14977307

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Richard Patten ,  Bernd Waidhas ,  Sonja Koller

IPC: H01L23/373 ,  H01L23/31

CPC classification number: H01L23/3736 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

Abstract: Embodiments herein may relate to a flip-chip chip scale package (FCCSP) with a thermal dissipation layer to dissipate heat from the FCCSP during operation of the FCCSP. The thermal dissipation layer may be applied to a surface of the FCCSP through a sputter coating process and may operate as a heat spreader for the FCCSP. Other embodiments may be described and/or claimed.

公开(公告)号：US20190072732A1

公开(公告)日：2019-03-07

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

CPC classification number: G02B6/428 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/43 ,  G02B2006/12197

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10209466B2

公开(公告)日：2019-02-19

申请号：US15089524

申请日：2016-04-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/30 ,  G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.