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    Semiconductor die package with more than one hanging die
    1.
    发明授权
    Semiconductor die package with more than one hanging die 有权

    公开(公告)号：US10854590B2

    公开(公告)日：2020-12-01

    申请号：US15776378

    申请日：2015-12-23

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Richard Patten ,  Georg Seidemann ,  Christian Geissler

    IPC: H01L23/02 ,  H01L25/00 ,  H01L25/065 ,  H05K1/11

    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

    Integrated circuit package assemblies including a chip recess
    2.
    发明授权
    Integrated circuit package assemblies including a chip recess 有权

    公开(公告)号：US10714455B2

    公开(公告)日：2020-07-14

    申请号：US16215449

    申请日：2018-12-10

    Applicant: Intel IP Corporation

    Inventor： Georg Seidemann ,  Klaus Reingruber

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L23/367 ,  H01L23/538

    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.

    INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS
    4.
    发明申请
    INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS 审中-公开

    公开(公告)号：US20180342431A1

    公开(公告)日：2018-11-29

    申请号：US15778410

    申请日：2015-12-18

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Christian Geissler ,  Georg Seidemann ,  Sonja Koller

    IPC: H01L23/13 ,  H01L23/498

    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.

    Interconnect structure for a microelectronic device
    6.
    发明授权
    Interconnect structure for a microelectronic device 有权

    公开(公告)号：US10366968B2

    公开(公告)日：2019-07-30

    申请号：US15282855

    申请日：2016-09-30

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

    ELECTRONIC PACKAGE WITH COIL FORMED ON CORE
    8.
    发明申请
    ELECTRONIC PACKAGE WITH COIL FORMED ON CORE 有权

    公开(公告)号：US20170162314A1

    公开(公告)日：2017-06-08

    申请号：US14956859

    申请日：2015-12-02

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

    IPC: H01F27/28 ,  H01F27/24

    CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

    Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

    INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE
    10.
    发明申请
    INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20190333886A1

    公开(公告)日：2019-10-31

    申请号：US16505307

    申请日：2019-07-08

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

    IPC: H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11

    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

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