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公开(公告)号：HK1038279A1
公开(公告)日：2002-03-08
申请号：HK01108703
申请日：2001-12-12
Applicant: KOREA ELECTRONICS TECHNOLOGY
Inventor： KIM JONG KYU , PARK IN SHIG , SEO HO SEOK
IPC: H01Q20060101
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公开(公告)号：HK1026072A1
公开(公告)日：2000-12-01
申请号：HK00105266
申请日：2000-08-22
Applicant: KOREA ELECTRONICS TECHNOLOGY
Inventor： KIM JONG KYU , PARK IN SHIG , SEO HO SEOK
Abstract: A multilayered helical antenna for mobile communication units includes a first dielectric sheet, a plurality of second dielectric sheets, a plurality of second and third dielectric sheets. All of the second dielectric sheets, except one, have a starting hole and an ending hole, with the exception having the starting hole only. Each of the second dielectric sheet is provided with a partially opened circular metallic pattern. Each of the third dielectric sheets has a via hole. Each of the dielectric sheets has a through-hole at a center thereof in order to allow a whip antenna to be slid upward and downward along a center axis of a helical antenna which is formed by stacking the dielectric sheets in a predetermined order. The via holes are filled with the same conducting material as the partially opened circular metallic patterns to thereby vertically connect the partially opened circular metallic patterns on the second dielectric sheets through the corresponding starting holes and ending holes, thereby forming a spiral capable of transmitting and receiving horizontal and vertical polarizations.
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公开(公告)号：DE69916761T2
公开(公告)日：2004-09-23
申请号：DE69916761
申请日：1999-11-04
Applicant: KOREA ELECTRONICS TECHNOLOGY , PILKOR ELECTRONICS LTD
Inventor： KANG NAM KEE , PARK IN SHIG , LIM WOOK , YOO CHAN SEI , KIM JONG DAE , KO HYUN JONG , KIM SANG CHEOL
Abstract: A multilayer type chip inductor includes a pair of outermost sheets each of which has a terminal pattern and a first via hole for an electrical connection with neighboring patterns and a plurality of intermediate sheets each of which has a conductor pattern, a second via hole for an electrical connection with neighboring patterns, and a first through hole for reducing a dielectric constant of the inductor. The intermediate sheets are stacked between the outermost sheets in such a way that the conductor patterns thereof are electrically connected with each other and simultaneously are electrically connected with the terminal patterns of the outermost sheets through the first and the second via holes.
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公开(公告)号：DE69916761D1
公开(公告)日：2004-06-03
申请号：DE69916761
申请日：1999-11-04
Applicant: KOREA ELECTRONICS TECHNOLOGY , PILKOR ELECTRONICS LTD
Inventor： KANG NAM KEE , PARK IN SHIG , LIM WOOK , YOO CHAN SEI , KIM JONG DAE , KO HYUN JONG , KIM SANG CHEOL
Abstract: A multilayer type chip inductor includes a pair of outermost sheets each of which has a terminal pattern and a first via hole for an electrical connection with neighboring patterns and a plurality of intermediate sheets each of which has a conductor pattern, a second via hole for an electrical connection with neighboring patterns, and a first through hole for reducing a dielectric constant of the inductor. The intermediate sheets are stacked between the outermost sheets in such a way that the conductor patterns thereof are electrically connected with each other and simultaneously are electrically connected with the terminal patterns of the outermost sheets through the first and the second via holes.
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