FABRICATION OF HIGH VOLTAGE POWER ELEMENT

    公开(公告)号:JPH11191624A

    公开(公告)日:1999-07-13

    申请号:JP29103998

    申请日:1998-10-13

    Abstract: PROBLEM TO BE SOLVED: To improve on-resistance by minimizing impurity diffusion of drift region and decreasing the length thereof using a TEOS oxide which is deposited through low temperature field oxide deposition process in the fabrication process of MOS high voltage power element. SOLUTION: A P-epitaxial layer 22 is implanted with phosphorous ions and heated treated to form a deep N-well 23, and an ion implanted mask defining a float region is formed thereon. Subsequently, P-type impurity ions are implanted and an ion-implanted mask defining an N-well is formed on the deep N-well 23 and then is heated-treated to form a P-type drift region 24 an N-well 25 abutting thereon. Thereafter, an oxide is deposited on the entire surface of the substrate, a primary TEOS oxide is deposited and heat treated, a thinner secondary TEOS oxide is further deposited thereon and etched to form a field oxide 26, in which a specified region is exposed in the active region of a power element.

    METHOD FOR MANUFACTURING PLANE TYPE ANTI-FUSE ELEMENT

    公开(公告)号:JPH1050842A

    公开(公告)日:1998-02-20

    申请号:JP33398396

    申请日:1996-12-13

    Abstract: PROBLEM TO BE SOLVED: To reduce loss of input energy for driving anti-fuse element by a method wherein an active layer is formed with a substance having low treatment temperature, and an insulation film is formed between the active layer and an electrode, composed of the insulation film having a uniform insulation breakdown voltage and a low insulation breakdown voltage. SOLUTION: On a silicon substrate 21, a first insulation film 22, a silicon- germanium layer 23a and a doped silicon-germanium layer 23b are formed. The doped silicon-germanium layer 23b is patterned to form silicon-germanium patterns 23 serving as an active layer. A second insulation layer 24 is formed on a first insulation film 22 containing the silicon-germanium patterns 23. It is etched to expose a surface of the silicon-germanium patterns 23, and a third insulation film 25 composed of TEOS is formed on the surface. Thereby, regulation in a thickness of the insulation film is facilitated and the degree of uniformity in a resistance value after programming can be enhanced.

Patent Agency Ranking