公开(公告)号：JPH1187310A

公开(公告)日：1999-03-30

申请号：JP20675098

申请日：1998-07-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN SOKI ,  KIN SHODAI ,  KU JIN-KUN ,  NAM KI-SU ,  RI DAIU ,  RO TAIBUN

IPC: H01L21/302 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To enable formation of an oxide film pattern the lateral side of which has a gentle degree of inclination, by selectively etching a multilayered oxide layer, and thus forming an oxide film pattern with an inclined sidewall. SOLUTION: After a first oxide film 302a is evaporated on a semiconductor substrate 301, heat treatment is carried out at a temperature of 200-1400 deg.C, and a second oxide film 302b is evaporated on the first oxide film 302a. In this case, the evaporation temperature of the second oxide film 302b is lower than the evaporation temperature of the first oxide film 302a. The lateral inclination of first and second oxide film patterns to be formed after etching is very moderate. This form is made because the second oxide film 302b is etched faster than the first oxide film 302a. That is, the first oxide film 302a and the second oxide film 302b of heterojunction are different in structure and physical characteristics. When these oxide films are etched by using the same etchant, the sidewalls of these oxide films have a very gentle inclination because the etching ratios differ from each other.

公开(公告)号：JPH11191624A

公开(公告)日：1999-07-13

申请号：JP29103998

申请日：1998-10-13

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN SHUDAI ,  KIN SOKI ,  KU JIN-KUN

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve on-resistance by minimizing impurity diffusion of drift region and decreasing the length thereof using a TEOS oxide which is deposited through low temperature field oxide deposition process in the fabrication process of MOS high voltage power element. SOLUTION: A P-epitaxial layer 22 is implanted with phosphorous ions and heated treated to form a deep N-well 23, and an ion implanted mask defining a float region is formed thereon. Subsequently, P-type impurity ions are implanted and an ion-implanted mask defining an N-well is formed on the deep N-well 23 and then is heated-treated to form a P-type drift region 24 an N-well 25 abutting thereon. Thereafter, an oxide is deposited on the entire surface of the substrate, a primary TEOS oxide is deposited and heat treated, a thinner secondary TEOS oxide is further deposited thereon and etched to form a field oxide 26, in which a specified region is exposed in the active region of a power element.

公开(公告)号：JPH11261066A

公开(公告)日：1999-09-24

申请号：JP34059598

申请日：1998-11-30

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI DAIU ,  RO TAIBUN ,  KU JIN-KUN ,  KIM JONG-DAE ,  KIN SOKI ,  NAM KI-SU

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To drop yield voltage and ON-resistance, by extending a gate electrode in a lateral direction to a part of the upper side of a field insulating film from a gate area along the upper side of the center of a drift area, and extending a source electrode to a part of the field insulating film of the upper side of the drift area from a source area. SOLUTION: The gate electrode 7 of an electric element has a gate field board structure extended to a part of a field insulating film 3 through the center of the upper side of an n-type drift area 4 from a gate area in a lateral direction. A source electrode 11 has a field board structure extended to a part of the interlayer insulating film 10 of the upper side of the n-type drift area 4 from a source area. Thus, a depletion layer in the drift area 4 at the time of an operation changes by drain voltage and gate voltage. Yield voltage is boosted by RESURF(reduced surface field) effect in the drift area given by a source field board. Then, ON-resistance is reduced by the reduction of the depletion layer by the gate field board.