MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

    公开(公告)号:JPH10233402A

    公开(公告)日:1998-09-02

    申请号:JP22004397

    申请日:1997-07-31

    Abstract: PROBLEM TO BE SOLVED: To remove the pollutant in a contact hole for enhancing the crystalline characteristics, by a method wherein a contact hole is coated with a metal to be buried in the contact hole so that the gathering step may be performed during the advancement of respective stages forming a metallic wiring by patterning process or after the completion of the stages. SOLUTION: A P well 22 is formed on a semiconductor substrate 21, and after growing a field oxide film 24, a gate insulating film 25 and a gate electrode 23 are formed. Next, in the stage finishing the formation of an interlayer insulating film 26 and a definite contact hole, the substrate underside is implanted with ions so as to perform the true gathering step by the thin film evaporation under the stress such as silicon nitride, etc., extensional gathering doing the physical damage by scratching.rapping, etc., or using either the rapid heat treatment or an electric furnace. Later, the partition wall metal and wiring metal evaporation step is advanced to form the patterns. Through these procedures, the semiconductor substrate on the contact hole underside can be made into a non-defective region, thereby enabling the crystal to be restored to the single crystalline level.

    METHOD FOR MANUFACTURING FINE STRUCTURE USING SACRIFICIAL LAYER

    公开(公告)号:JPH10107339A

    公开(公告)日:1998-04-24

    申请号:JP18239897

    申请日:1997-07-08

    Abstract: PROBLEM TO BE SOLVED: To prevent the sealing phenomenon of a silicon first structure, due to the elimination of a sacrifice layer by eliminating the sacrificial oxide layer by performing etching with a steam phase atmosphere that contains a steam of HF anhydride and methanol. SOLUTION: An oxide film 32 and a nitride film 33 are deposited on a silicon substrate 31, and a first polysilicon film 37 is deposited on the nitride film 33. Then, a first TOSE film pattern is formed on the first polysilicon film 37 as a sacrificial layer for providing a space for forming a fine structure, and a second polysilicon film 35 that is the material of the fine structure is deposited. Then, a second TOSE film is deposited as the mask of the second polysilicon film 35, the second polysilicon film 35 is subjected to dry etching selectively, a fine structure pattern is formed, and then a photoresist is eliminated. After that, it is arranged in a space that is filled with the steam of HF anhydride and methanol, and the exposed first TOSE film pattern is subjected to steam phase etching by the HF anhydride and methanol, thus forming a space 100.

    METHOD FOR MANUFACTURING PLANE TYPE ANTI-FUSE ELEMENT

    公开(公告)号:JPH1050842A

    公开(公告)日:1998-02-20

    申请号:JP33398396

    申请日:1996-12-13

    Abstract: PROBLEM TO BE SOLVED: To reduce loss of input energy for driving anti-fuse element by a method wherein an active layer is formed with a substance having low treatment temperature, and an insulation film is formed between the active layer and an electrode, composed of the insulation film having a uniform insulation breakdown voltage and a low insulation breakdown voltage. SOLUTION: On a silicon substrate 21, a first insulation film 22, a silicon- germanium layer 23a and a doped silicon-germanium layer 23b are formed. The doped silicon-germanium layer 23b is patterned to form silicon-germanium patterns 23 serving as an active layer. A second insulation layer 24 is formed on a first insulation film 22 containing the silicon-germanium patterns 23. It is etched to expose a surface of the silicon-germanium patterns 23, and a third insulation film 25 composed of TEOS is formed on the surface. Thereby, regulation in a thickness of the insulation film is facilitated and the degree of uniformity in a resistance value after programming can be enhanced.

Patent Agency Ranking