公开(公告)号：JPH0738118A

公开(公告)日：1995-02-07

申请号：JP32429293

申请日：1993-12-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU JIYUNKOU ,  HAKU TANEYASU ,  MINAMI MOTOMORI

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE: To form a good polycrystalline Si film on a substrate by creating crystal nuclei in an amorphous Si film on the substrate at specified high temp. or more and separating a step of growing crystal grains at a specified low temp. or less to crystallize it. CONSTITUTION: On a wafer 31 having a silicon oxide film 32 an amorphous Si film 33 is formed and heat-treated at 600 deg.C or more for a short time to create crystal nuclei of adequate density and size in a quickly heat-treating chamber, crystal grains already created in an electric furnace are grown at 600 deg.C or less to form a good polycrystalline Si. When the crystal grain growth is made at 600 deg.C or lower, because the temp. dependence of the crystal nucleus creating is higher than that of the crystal grain growth, new crystal nucleus generation is fully suppressed to form a good polycrystal Si film 33 uniform in the crystal grain.

公开(公告)号：JPH08186262A

公开(公告)日：1996-07-16

申请号：JP31538294

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU JIYUNKOU ,  BOKU KEIKOU ,  MINAMI MOTOMORI

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: PURPOSE: To enhance productivity by providing steps for forming a high quality polysilicon thin film and an oxide film from an amorphous silicon thin film and for defining an active region and a gate oxide film by patterning both films thereby shortening the required time of a step for crystallizing the amorphous silicon in a solid phase. CONSTITUTION: An intrinsic amorphous silicon layer is deposited on an insulating board 51 in the first step. In the second step, an amorphous silicon thin film is heat treated in an electric furnace of a high pressure oxygen atmosphere to deposit a polysilicon 52 and an oxide 53. In the third step, the polysilicon 52 and the oxide 53 are patterned to define the active region of TFT. In the fourth step, a side wall oxide 53+ is deposited on the side wall of the polysilicon 52 and the oxide 53. In the fifth step, a gate electrode and a source- drain region are formed. Finally, interconnection step of a metal oxide 57 is carried out thus completing a Poly-Si TFT.