公开(公告)号：JPH0738118A

公开(公告)日：1995-02-07

申请号：JP32429293

申请日：1993-12-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU JIYUNKOU ,  HAKU TANEYASU ,  MINAMI MOTOMORI

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE: To form a good polycrystalline Si film on a substrate by creating crystal nuclei in an amorphous Si film on the substrate at specified high temp. or more and separating a step of growing crystal grains at a specified low temp. or less to crystallize it. CONSTITUTION: On a wafer 31 having a silicon oxide film 32 an amorphous Si film 33 is formed and heat-treated at 600 deg.C or more for a short time to create crystal nuclei of adequate density and size in a quickly heat-treating chamber, crystal grains already created in an electric furnace are grown at 600 deg.C or less to form a good polycrystalline Si. When the crystal grain growth is made at 600 deg.C or lower, because the temp. dependence of the crystal nucleus creating is higher than that of the crystal grain growth, new crystal nucleus generation is fully suppressed to form a good polycrystal Si film 33 uniform in the crystal grain.

公开(公告)号：JPH08160406A

公开(公告)日：1996-06-21

申请号：JP31506894

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： MINAMI MOTOMORI ,  BOKU SHINSHIYOU ,  KIN HISAHIRO ,  BOKU SOUSHIYUN

IPC: G02F1/1333 ,  G02F1/13 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/35 ,  H01L21/336 ,  H01L29/786

Abstract: PURPOSE: To provide a method for manufacturing a large area flat display utilizing side joint, so as to obtain a large area via the use of the side jointing method. CONSTITUTION: A product technology for realizing a large screen by use of the thin film transistor technology is provided under the application of the entirely unique method of side jointing. In this case, a thin film transistor unit panel 2 is manufactured through a process for the side jointing to form a large area at a side jointing process, and a process for jointing a large area thin film transistor panel 4 to a common electrode panel 5.

公开(公告)号：JPH07201806A

公开(公告)日：1995-08-04

申请号：JP29182194

申请日：1994-11-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： YASU KINEI ,  BOKU KEIKOU ,  MINAMI MOTOMORI ,  KIYOU SOUGEN

IPC: B41J2/135 ,  B44C1/22 ,  B44C3/00 ,  B81C1/00 ,  G02B1/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L29/84

Abstract: PURPOSE: To manufacture a structure which has a mechanical function into various constitution by combining together identical substrate or different kind substrate jointing technology and selective anisotropic etching technology and decreasing photographic transfer processes. CONSTITUTION: After a [110] substrate 110 and a [100] substrate 1102 are jointed together, the 100 substrate 1102 is formed into a thin film. On one surface of a substrate 1101, an etching protection mask 1103 is formed to form an etching window 1104. This is etched anisotropically in a KOH and EDP solution, and the etching is advanced while a [111] surface 1105 is exposed at right angles to the substrate surface. After the substrate 1101 is etched into a quadrilateral prism, the etching is continued on, while the bottom surface 1107 of the formed quadrilateral is regarded as an etching window. Then the etching advances only to the substrate 1102 positioned below the bottom surface 1107, and when a [111] sidewall 1108 is exposed, the etching is suppressed to form a truncated pyramidal structure 1109. A nozzle is thus manufactured.

公开(公告)号：JPH08186262A

公开(公告)日：1996-07-16

申请号：JP31538294

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU JIYUNKOU ,  BOKU KEIKOU ,  MINAMI MOTOMORI

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: PURPOSE: To enhance productivity by providing steps for forming a high quality polysilicon thin film and an oxide film from an amorphous silicon thin film and for defining an active region and a gate oxide film by patterning both films thereby shortening the required time of a step for crystallizing the amorphous silicon in a solid phase. CONSTITUTION: An intrinsic amorphous silicon layer is deposited on an insulating board 51 in the first step. In the second step, an amorphous silicon thin film is heat treated in an electric furnace of a high pressure oxygen atmosphere to deposit a polysilicon 52 and an oxide 53. In the third step, the polysilicon 52 and the oxide 53 are patterned to define the active region of TFT. In the fourth step, a side wall oxide 53+ is deposited on the side wall of the polysilicon 52 and the oxide 53. In the fifth step, a gate electrode and a source- drain region are formed. Finally, interconnection step of a metal oxide 57 is carried out thus completing a Poly-Si TFT.

公开(公告)号：JPH05326854A

公开(公告)日：1993-12-10

申请号：JP27369991

申请日：1991-10-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  GU YOUSHIYO ,  KIN KOUSHIYU ,  MINAMI MOTOMORI

IPC: H01L21/8249 ,  H01L27/06

Abstract: PURPOSE: To reduce the capacitive components of parts by reducing the inactive base region of a bipolar transistor and source-drain region of a CMOS transistor. CONSTITUTION: This method comprises the steps of depositing a crystal Si film 8, oxide film 9 and nitride film 10 to form emitters and collectors of bipolar elements and gates of CMOS elements, forming an oxide film 11 and second oxide film 12 at both side faces of a polycrystalline Si film 18, etching the exposed surface of an epitaxial layer 3, forming a third nitride film 13 on the side faces of a second nitride film, growing an oxide film 14 on the epitaxial layer 3, removing the nitride films 10, 12, 13 to expose an epitaxial layer 16, implanting impurities in this layer 16 to form p -type regions portions 17 for forming base regions of the bipolar elements and source and drain regions of PMOS elements, and forming n -type regions at portions 18 for forming source and drain regions of NMOS elements.