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    Object transport and position monitoring method
    2.
    发明专利
    Object transport and position monitoring method 未知

    公开(公告)号：DE19755142A1

    公开(公告)日：1999-06-02

    申请号：DE19755142

    申请日：1997-12-11

    Applicant: KROENKE MATTHIAS

    Inventor： KROENKE MATTHIAS

    IPC: G01C21/00 ,  G08G1/123 ,  G08G1/127 ,  G01C21/02 ,  G01N15/00

    Abstract: The method uses a miniature HF transmitter (2) in the form of a chip card incorporated in the monitored object (1), for providing a data telegram identifying the object at programmed time intervals, received by a reception station (5) for a GSM communications network and/or geostationary satellites, for determining each position of the object. The object position can be transmitted to a central computer upon verification of an interrogation code, with a tariff charge calculated for each interrogation. An Independent claim for a transport and position monitoring system is also included.

    METHOD AND SYSTEM FOR MONITORING THE TRANSPORTATION AND POSITIONING OF MOVING OBJECT
    4.
    发明专利
    METHOD AND SYSTEM FOR MONITORING THE TRANSPORTATION AND POSITIONING OF MOVING OBJECT 未知

    公开(公告)号：CA2252997A1

    公开(公告)日：1999-05-28

    申请号：CA2252997

    申请日：1998-11-06

    Applicant: KROENKE MATTHIAS

    Inventor： KROENKE MATTHIAS

    IPC: G08B13/22 ,  G08G1/127 ,  H04B1/59 ,  H04W64/00 ,  G01S5/14 ,  G08B15/00 ,  H04Q7/22

    Abstract: The invention relates to a method and a system for monitoring the transportation and positioning of moving objects, a miniaturised high frequency transmitter being attached first of all to the object and the high frequency transmitter after clearance sending a data telegram in pre-set programmable intervals of time, the data telegram clearly identifying the object. The data telegrams are received by reception stations of a preferably GSM telecommunication network and/or from geostationary location satellites. The received data are stored and serve to locate the respective transmission place via radio cells of the GSM network and/or of the satellite location system. The stored data about the position or the transport route of the respective object are then transmitted upon inquiry and after identification by pre-setting and checking of a code word. The data storage for a multiplicity of objects is achieved by means of a central computer which is used at the same time for calculating and billing of costs per inquiry.

    METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
    5.
    发明申请
    METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT 审中-公开
    方法制造集成电路

    公开(公告)号：WO02089202A3

    公开(公告)日：2003-02-20

    申请号：PCT/EP0204067

    申请日：2002-04-11

    Applicant: INFINEON TECHNOLOGIES AG ,  GUSTIN WOLFGANG ,  WANG KAE-HORNG ,  KROENKE MATTHIAS

    Inventor： GUSTIN WOLFGANG ,  WANG KAE-HORNG ,  KROENKE MATTHIAS

    IPC: H01L21/283 ,  H01L21/302 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521

    Abstract: The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height on the surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first, second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (F2a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (F2c) above the common active area (60), partially overlapping the first and second gate stack (GS1, GS2), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask (32) in an etching process, the first contact hole (KB) uncovering the common active area (60) on the surface of the substrate between the first and second gate stack (GS1, GS2), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS2, GS2) and the third contact hole (KG) uncovering the upper side of the gate connection (20) of the third gate stack (GS3).

    Abstract translation: 本发明提供了一种制造包括以下步骤的集成电路的方法，包括：为包括以下步骤的集成电路的制造过程：提供衬底（1）具有至少第一，第二和第三规定的基板表面上约等于高栅极堆叠（GS1，GS2 ，GS3），其特征在于，提供了一种公共有源区（60）在所述第一和第二栅极堆叠（GS1，GS2）之间的衬底（1）在基板表面上; 用于覆盖嵌入所述第一，第二和第三栅极堆叠（GS1，GS2，GS3）提供第一绝缘层（70）; 暴露第三栅极堆叠（GS3）的栅极端子（20）的顶表面上; 用于覆盖的栅极端子的顶部（20）提供的第二绝缘层（80）; 提供具有上述第三和之间的第三栅极堆叠（GS3），第二开口（F2B）在基板上面（1）的栅极端子（20）的暴露的上表面上的第一开口（素F2α）在所得到的结构的掩模（M2） 具有第二栅极堆叠（GS3，GS2）和公共有源区（60），其部分地重叠第一和第二栅极堆叠（GS1，GS2）上方的第三开口（F2C）; 和同时形成第一，第二和第三接触孔（KB，KS，KG）通过使用掩模（M2）的蚀刻过程中，所述第一接触孔（KB），以在第一和第二之间的衬底表面上的公共有源区（60） 栅极堆叠（GS1，GS2），第二接触孔（KS）中，第二和第三栅极堆叠（GS2，GS2）和第三接触孔（KG）的第三栅极堆叠的栅极端子（20）的上表面之间的衬底表面（GS3）覆盖。

    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS
    6.
    发明申请
    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS 审中-公开
    用于生产FERRO电气电容和集成半导体内存块

    公开(公告)号：WO02065518A3

    公开(公告)日：2002-11-21

    申请号：PCT/DE0104790

    申请日：2001-12-18

    Applicant: INFINEON TECHNOLOGIES AG ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

    CPC classification number: H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    Abstract: The invention relates to a method for the production of ferroelectric capacitors structured according to the stack principle, which are used in integrated semiconductor memory chips, wherein the individual capacitor modules (10, 11) have an oxygen barrier (4a, 4b) between a lower capacitor electrode (5a, 5b) and an electrically conductive plug (1a, 1b). At a site where it is not covered by the corresponding oxygen barrier (4a, 4b), an unstructured adhesive layer (3) is oxidized by the oxygen arising during the tempering process of the ferroelectric (6a, 6b) and forms insulating segments at said site in such a way that the lower capacitor electrodes (5a, 5b) of the ferroelectric capacitors (10, 11) are electrically insulated from one another. This makes it possible to eliminate the structuring step of the adhesive layer (3). Furthermore, said layer (3) serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

    Abstract translation: 在用于生产在堆栈原则强电介质电容器建成为在集成的半导体存储器装置中使用的方法，所述个别电容器模块（10，11）具有氧阻隔（4A，4B）的下电容器电极之间（5A，5B）和导电插头（1A， 图1b）。 非结构化Hafschicht（3），在那里它们（4A，4B）是通过在铁电体的退火过程中的氧所覆盖的相应的氧屏障的不（6A，6B）形成，氧化的和形式的绝缘部分，使得下 电容器电极（图5a中，铁电电容器（10的​​5B9，11）彼此电绝缘。这消除了对粘接剂层（3），并且还，该层（3）可以被用于堵塞用于吸杂氧和抑制氧气扩散的图案化步骤。

    METHOD FOR THE PRODUCTION OF CONTACTS FOR INTEGRATED CIRCUITS AND SEMICONDUCTOR COMPONENT WITH SAID CONTACTS
    7.
    发明申请
    METHOD FOR THE PRODUCTION OF CONTACTS FOR INTEGRATED CIRCUITS AND SEMICONDUCTOR COMPONENT WITH SAID CONTACTS 审中-公开
    工艺用于生产集成电路和半导体元件这样的联系联系

    公开(公告)号：WO03007355A3

    公开(公告)日：2003-09-18

    申请号：PCT/EP0207507

    申请日：2002-07-05

    Applicant: INFINEON TECHNOLOGIES AG ,  KROENKE MATTHIAS ,  STAUB RALF ,  WANG KAE-HORNG

    Inventor： KROENKE MATTHIAS ,  STAUB RALF ,  WANG KAE-HORNG

    IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/28

    CPC classification number: H01L27/10888 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10829

    Abstract: The invention relates to the production of one (or several) contacts on one or several active areas of a semiconductor disk, whereby one or several insulated control lines can be arranged on the active areas to be contacted. The control lines can, for example, be gate lines. The semiconductor element is produced in the following manner: a polysilicon layer is deposited on the semiconductor disk, the polysilicon layer is structured in order to produce a polysilicon contact over the active area, whereby the polysilicon contact covers the two control lines in an at least partial manner, a first insulator layer is applied to the semiconductor disk incorporating said polysilicon contact, the first insulator layer is partially removed to reveal the covering surface of the polysilicon contact and a metal layer is applied to the semiconductor disk for the electrical contacting of the polysilicon contact.

    Abstract translation: 有在半导体晶片的一个或多个有源区，其中一个或多个分离的控制线可以被布置在有源区域的一个（或更多个）触点被接触生成。 控制线可以是，例如，到栅极线。 的半导体器件如下制造：在多晶硅接触的嵌入在半导体晶片上沉积多晶硅层，图案化多晶硅层以形成在所述有源区中的多晶硅接触，其中，所述多晶硅接触至少覆盖两条控制线部分，在半导体晶片上施加第一绝缘层 ，部分去除所述第一绝缘层以暴露该多晶硅接触的顶部表面和该半导体晶片上施加金属层用于使多晶硅接触的电接触。

    METHOD FOR PRODUCING FERROELECTRIC MEMORY CELLS
    8.
    发明申请
    METHOD FOR PRODUCING FERROELECTRIC MEMORY CELLS 审中-公开
    用于生产FERRO电记忆CELL

    公开(公告)号：WO02078084A2

    公开(公告)日：2002-10-03

    申请号：PCT/DE0201054

    申请日：2002-03-22

    Applicant: INFINEON TECHNOLOGIES AG ,  KASKO IGOR ,  KROENKE MATTHIAS

    Inventor： KASKO IGOR ,  KROENKE MATTHIAS

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246

    CPC classification number: H01L21/76855 ,  H01L21/7687 ,  H01L21/76888 ,  H01L28/55 ,  H01L28/75

    Abstract: The invention relates to a method for producing ferroelectric memory cells in accordance with the stack principle. According to said method, an adhesive layer (2, 3) is formed between a lower capacitor electrode (6) of a memory capacitor and a conductive plug (1), which is formed below said electrode and makes an electric connection between said capacitor electrode (6) and a transistor electrode of a selection transistor that is formed in or on a semiconductor wafer. An oxygen diffusion barrier (4, 5) is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. The method is characterised by the following steps: (A) Determination of the oxygen speed of the adhesive layer (2, 3) and the diffusion coefficient (DOxygen(T)) of oxygen in the material of the adhesive layer (2, 3), dependent on the temperature (T); (B) Determination of the diffusion coefficient (DSilicon(T)) of silicon in the material of the adhesive layer (2, 3), dependent on the temperature and (C) Calculation of an optimal temperature range for the RTP step from the two diffusion coefficients, (DOxygen(T)) and (DSilicon(T)) that have been determined for a predetermined layer thickness (dBARR) and layer width (bBARR) of the layer system consisting of the adhesive layer and the oxygen diffusion barrier, so that during the RTP step the siliconisation of the adhesive layer occurs more rapidly than its oxidation.

    Abstract translation: 本发明涉及一种用于铁电存储器单元的制备根据堆栈原则，其中，下电容器电极（6）之间的存储电容器和底层形成的导电插塞（1），用于电连接所述（6），其具有一个的晶体管电极电容器电极中或上 走秀半导体晶片选择晶体管形成，粘接层（2，3）和粘合剂层的氧扩散阻挡层（4,5）形成，并进行强电介质的沉积之后的RTP步骤在氧气气氛中，所述方法的特征在于以下步骤：（ A）测定，所述粘合剂层的氧化速率（2，3）和扩散系数（DSauerstoff（T）在粘合剂层（2的材料中的氧的），3）中的温度（T）的依赖性; （B）在所述粘合剂层的材料中的硅的扩散系数（DSilizium（T））的计算（2,3）（取决于温度和（C）计算最优的温度范围内，用于从先前确定的两个扩散系数的RTP步骤DSauerstoff （T）和DSilizium（T））（对于给定的层厚度dBARR）和氧扩散阻挡，使得在RTP步骤中，粘合剂层的硅化比其氧化得更快。

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