公开(公告)号：KR20200126011A

公开(公告)日：2020-11-05

申请号：KR20207030669

申请日：2019-03-18

Applicant: LAM RES CORP

Inventor： YU JENGYI ,  TAN SAMANTHA SIAMHWA ,  VOLOSSKIY BORIS ,  KOLICS ARTUR ,  PAN YANG

IPC: H01L21/285 ,  C23C16/44 ,  H01L21/02 ,  H01L21/324 ,  H01L21/67

Abstract: 기판상에금속상호접속층을증착하는방법은프로세싱챔버의기판지지부상에기판을배치하는단계및 접착층, 확산배리어, 및시드층 중적어도하나로서기능하도록구성된중간층을기판상에증착하는단계를포함한다. 중간층을증착하는단계는금속-실리사이드 (M-Si) 결합을갖는제 1 재료를포함하는금속-유기전구체를공급하는것을포함한다. 방법은중간층 상에금속상호접속층을증착하는단계를더 포함한다.

公开(公告)号：SG11202110310RA

公开(公告)日：2021-10-28

申请号：SG11202110310R

申请日：2020-03-16

Applicant: LAM RES CORP

Inventor： HENRI JON ,  COLINJIVADI KARTHIK S ,  ROBERTS FRANCIS SLOAN ,  REDDY KAPU SIRISH ,  TAN SAMANTHA SIAMHWA ,  LEE SHIH-KED ,  HUDSON ERIC ,  SCHROEDER TODD ,  YANG JIALING ,  ZHENG HUIFENG

IPC: H01L21/3065 ,  C23C16/04 ,  C23C16/26 ,  C23C16/50 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67

Abstract: Fabricating a semiconductor substrate by (a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate and (b) depositing an amorphous carbon liner onto the sidewalls of the feature. Steps (a) and optionally (b) are iterated until the vertical etch feature has reached a desired depth. With each iteration of (a), the feature is vertical etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. With each optional iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is replenished.