CMOS GATE STRUCTURE
    2.
    发明专利

    公开(公告)号:JPH11289017A

    公开(公告)日:1999-10-19

    申请号:JP33315098

    申请日:1998-11-24

    Abstract: PROBLEM TO BE SOLVED: To obtain a CMOS gate structure in which a dopant does not creep at all treatment temperatures, by a method wherein a silicide which is annealed and treated is formed of large particle-size polysilicon of a lower multilayer structure. SOLUTION: After a polysilicon multilayer structure 20 is formed, a silicide layer 22 (WSix ) is deposited. The silicide layer 20 has a thickness of 50 Åor lower. After that, the silicide layer 22 is annealed and treated in an NH3 atmosphere, and the silicide layer 22 is nitrided. The silicide layer 22 functions as an intermediate dopant barrier layer in a final gate stack structure. After that, the second bulk deposition of the silicide layer 22 is performed, and a silicide layer 24 is deposited on the silicide layer 22 which has become the barrier layer. After that, a final annealing treatment is performed, the silicide layer 22 and the silicide layer 24 form a structure similar to the structure of the particle size of the polysilicon multilayer structure 20. Since the particle size is uniform, a dopant does not creep to the structure 20 irrespective of a treatment temperature.

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