公开(公告)号：JP2000232224A

公开(公告)日：2000-08-22

申请号：JP3256099

申请日：1999-02-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NABESHIMA TAMOTSU ,  MATSUI YASUSHI

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To raise the breakdown voltage of a high-breakdown voltage field effect transistor (DMOSFET). SOLUTION: This semiconductor device is constituted into a structure, wherein a gate electrode 106C for DMOS is formed on an N-type epitaxial layer 101 on a semiconductor substrate 100. After a P-type body layer 107 is formed in such a way as to extend up to under the lower part of the electrode 106C in the side on one side of the sides of the electrode 106C on the layer 101, a source layer 109 for DMOS having an N-type first low-concentration impurity layer 109a, and an N-type first high-concentration impurity layer 109b which is encircled with the layer 109a, is formed in such a way that the layer 109 is encircled with the layer 107. A drain layer 110 for DMOS is formed in such a way that the layer 110 is separated from the electrode 106 on the other side of the electrode 106C on the layer 101. A source electrode 115 is formed in such a way that the end parts of the electrode 106C are covered with the electrode 115.

公开(公告)号：JP2000236092A

公开(公告)日：2000-08-29

申请号：JP3775799

申请日：1999-02-16

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NABESHIMA TAMOTSU ,  MATSUI YASUSHI

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To increase the breakdown voltage of a semiconductor device without increasing the number of processes, and to provide an HVMOS that can be mixedly mounted, a semiconductor device using it, and its manufacturing method. SOLUTION: On an n-epitaxial layer 1, p field relaxation layer and p-well layer 2 and 3, and n-well layers 4 and 5 are formed simultaneously. Then, a LOCOS oxide film 6 is formed, and p low-concentration diffusion layers 7 and 8 are formed simultaneously. A gate oxide film 9 and a gate polysilicon film 10 are formed successively, and a sidewall 11 is used for simultaneously forming an n-source/drain region 12 and an n-well region 13, and p-source/drain regions 14 and 15. Finally, a first interlayer insulating film 16 is formed, source/drain electrodes 17, 18, and 19 are formed simultaneously, and a second interlayer insulation 20 and a second drain electrode 21 are formed successively. The source electrode 18 is formed, while the source electrode covers the entire gate polysilicon film 10, and the second drain electrode 21 is formed so as to overlap with the end of the source electrode 18.

公开(公告)号：JPH08314406A

公开(公告)日：1996-11-29

申请号：JP11866095

申请日：1995-05-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO KOJI ,  MAE HAJIME ,  MATSUI YASUSHI

IPC: G09G3/282 ,  G09G3/20 ,  G09G3/296 ,  G09G3/28

Abstract: PURPOSE: To reduce the cost and power consumption of a driving device for a gas discharge type display device. CONSTITUTION: Semiconductor switches 61 -6N are connected between each cathode K1 -KN and a common line X0 , the common line X0 is driven by a push-pull circuit 1 consisting of semiconductor switches FP, FN, and a power collection circuit 4 is connected to the common line X0 . A semiconductor switch FP is turned on only in the last and short period of a driving period TP for each cathode K1 -KN, and a semiconductor switch FN is turned on two times in a off period of the semiconductor switch FP in a driving period TP. When a scanning pulse voltage is applied, semiconductor switches 61 -6N are turned on in an previous ON period of the semiconductor switch FN, when holding pulse voltage is applied, semiconductor switches 61 -6N are turned on in an ON period succeeding the semiconductor switch FN and an OFF period before and after it, power collection operation is performed by the power collection circuit 4 in a period when the semiconductor switch FP is turned off and the semiconductor switch FN is turned off.

公开(公告)号：JPH0574787A

公开(公告)日：1993-03-26

申请号：JP23143691

申请日：1991-09-11

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MATSUI YASUSHI ,  KIHARA HIDEYUKI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE:To obtain a bipolar type magnetic transistor which is high than a conventional multi-collector transistor in sensitivity by method wherein collector regions are provided and a region which of the same conductivity type as a base region and higher than in impurity concentration is provided to a part of the base region adjacent to an emitter region. CONSTITUTION:A contact region 5 is formed on a base region 3, an L-shaped and an inverted L-shaped P -type impurity diffused collector regions 6 and 7 are provided adjacent to the contact region 5 confronting each other. Furthermore, a P -type impurity diffused emitter region 8 is provided on the opposite side of the impurity diffusion layer 5. An N impurity diffusion layer 9 higher than the base region 3 in impurity concentration is formed on a region which is sandwiched between the collector regions 6 and 7 and located on the side of the emitter region 8. By this setup, a magnetic induction element of high sensitivity can be easily obtained.

公开(公告)号：JPH10340910A

公开(公告)日：1998-12-22

申请号：JP14905397

申请日：1997-06-06

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MATSUI YASUSHI

IPC: H01L29/41 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To realize a semiconductor device which enables reduction in the output resistance of elements in the case, where a plurality of elements are integrated on one semiconductor substate by using the same semiconductor process technique. SOLUTION: Two elements isolated by a P-type isolation layer 2 are produced on an N-type semiconductor substrate 1 by using the same semiconductor process technique. A bipolar transistor, as one of the elements, has a P-type base region 3 and an N-type emitter region 4 as its main parts, and an aluminum electrode 13 which is connected with a terminals electrode 15 and to be a collector lead-out electrode is formed on a surface of the N-type semiconductor substrate 1, which is different from the surface where tungsten electrodes 8 are formed as a base lead-out electrode and an emitter lead-out electrode. Another double diffused MOS transistors, has an N-type source region 6, a P-type back gate region 7 and a gate electrode 5 as its main parts, and an aluminum electrode 13 which is to be a drain lead-out electrode is formed on the surface of the N-type semiconductor substrate 1 which differs from the surface, where a tungsten electrode 8 is formed as a source lead-out electrode.