公开(公告)号：DE69231227T2

公开(公告)日：2001-03-01

申请号：DE69231227

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： BERMAN ERIC ,  ITALIANO GREG ,  PADGAONKAR AJAY ,  ALLEN RAY

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G06F11/20 ,  G11C29/00

公开(公告)号：DE69231227D1

公开(公告)日：2000-08-10

申请号：DE69231227

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： BERMAN ERIC ,  ITALIANO GREG ,  PADGAONKAR AJAY ,  ALLEN RAY

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G06F11/20 ,  G11C29/00

公开(公告)号：EP0612422A4

公开(公告)日：1996-05-22

申请号：EP92924264

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： BERMAN ERIC ,  ITALIANO GREG ,  PADGAONKAR AJAY ,  ALLEN RAY

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G06F15/20

CPC classification number: G06F9/30145 ,  G06F9/30167 ,  G06F11/2236 ,  G06F11/261 ,  G06F15/7814

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

公开(公告)号：EP0847573A4

公开(公告)日：1999-10-27

申请号：EP97931324

申请日：1997-06-27

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY ,  ALLEN RAY

IPC: G02F1/133 ,  G06F3/147 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

CPC classification number: G06F3/147 ,  G09G3/18 ,  G09G3/3696

Abstract: A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches (150-153) and a single slave data storage latch (154) shared by all of the plurality of master storage latches (150-153). A microcontroller has a central processing unit (CPU) for communicating with the master storage latches (150-153) via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch (154) with data from each of the master storage latches (150-153) and downloads the updated data from the single slave storage latch (154) to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch.