公开(公告)号：AT540460T

公开(公告)日：2012-01-15

申请号：AT08851188

申请日：2008-11-21

Applicant: MICROCHIP TECH INC

Inventor： DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

IPC: H02H9/04 ,  H01L27/02

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

公开(公告)号：AT540461T

公开(公告)日：2012-01-15

申请号：AT08852419

申请日：2008-11-21

Applicant: MICROCHIP TECH INC

Inventor： DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

IPC: H02H9/04 ,  H01L27/02

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

公开(公告)号：WO2009067673A3

公开(公告)日：2009-07-09

申请号：PCT/US2008084365

申请日：2008-11-21

Applicant: MICROCHIP TECH INC ,  DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

Inventor： DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

公开(公告)号：WO2009067672A3

公开(公告)日：2009-07-09

申请号：PCT/US2008084362

申请日：2008-11-21

Applicant: MICROCHIP TECH INC ,  DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

Inventor： DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract translation: 器件接口的自适应静电放电（ESD）保护在处理或安装到系统或从系统中移除时具有良好的ESD稳健性。 并且在系统中运行时，对DPI，电磁干扰（EMI）等具有强大的抗干扰能力。 在ESD保护金属氧化物半导体（MOS）器件的漏极和栅极之间存在显着的电容耦合，以在外部连接上没有（或低电平）DPI需要保护的情况下增强ESD保护并降低其回击电压 。 因此，当在外部连接上检测到显着的DPI / EMI信号时，MOS ESD保护装置的漏极和栅极之间的电容耦合被断开，旁路或衰减，从而增强了装置的DPI / EMI抗干扰性。