2.
    发明专利
    未知

    公开(公告)号:AT540461T

    公开(公告)日:2012-01-15

    申请号:AT08852419

    申请日:2008-11-21

    Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

    3.
    发明专利
    未知

    公开(公告)号:AT522860T

    公开(公告)日:2011-09-15

    申请号:AT00915025

    申请日:2000-03-23

    Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

    4.
    发明专利
    未知

    公开(公告)号:AT540460T

    公开(公告)日:2012-01-15

    申请号:AT08851188

    申请日:2008-11-21

    Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

    5.
    发明专利
    未知

    公开(公告)号:AT478478T

    公开(公告)日:2010-09-15

    申请号:AT05736311

    申请日:2005-04-15

    Abstract: A remote keyless entry (RKE) transponder has a programmable selective wake-up filter for determining whether the RKE transponder should wake-up to process a received signal. The wake-up filter correlates the timing of an input signal's carrier amplitude on and off time periods to a predefined programmable time period profile for a desired signal which has a certain carrier on time (time period on) and a certain carrier off time (time period off) arranged into a coded “header.” When a received signal matches the predefined time period profile, then the RKE transponder will wake-up to process the incoming signal data. The predefined time period profile may be programmable and may be stored in a header configuration register. Each RKE transponder has unique predefined time period on and time period off profiles.

    PROGRAM MEMORY SOURCE SWITCHING FOR HIGH SPEED AND/OR LOW POWER PROGRAM EXECUTION IN A DIGITAL PROCESSOR
    6.
    发明申请
    PROGRAM MEMORY SOURCE SWITCHING FOR HIGH SPEED AND/OR LOW POWER PROGRAM EXECUTION IN A DIGITAL PROCESSOR 审中-公开
    程序存储器源切换用于数字处理器中的高速和/或低功率程序执行

    公开(公告)号:WO2007048024A3

    公开(公告)日:2007-06-07

    申请号:PCT/US2006041218

    申请日:2006-10-19

    CPC classification number: G06F12/06 G06F12/0638 Y02D10/13

    Abstract: An integrated circuit digital processor is coupled to either a main program memory or a secondary program memory, wherein the secondary program memory may be low power, high reliability, non-volatile and/or fast memory that may store a limited number of critical program instructions and data for execution by the digital processor. A program memory switch may couple the digital processor to either the main program memory or the secondary program memory. This is particularly advantageous in that the secondary program memory may have attributes not economically feasible with the main program memory. A program memory controller may handle the selection of which of these memories that the digital processor is using to obtain its program instructions, and necessary control signals for switching and operation thereof.

    Abstract translation: 集成电路数字处理器耦合到主程序存储器或辅助程序存储器,其中辅助程序存储器可以是低功率,高可靠性,非易失性和/或快速存储器,其可以存储有限数量的关键程序指令 和由数字处理器执行的数据。 程序存储器开关可以将数字处理器连接到主程序存储器或辅助程序存储器。 这是特别有利的,因为次程序存储器可能具有主程序存储器在经济上不可行的属性。 程序存储器控制器可以处理选择数字处理器正在使用哪些存储器来获得其程序指令以及用于开关和操作的必要控制信号。

    ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION OF DEVICE INTERFACE FOR LOCAL INTERCONNECT NETWORK (LIN) BUS AND THE LIKE
    8.
    发明申请
    ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION OF DEVICE INTERFACE FOR LOCAL INTERCONNECT NETWORK (LIN) BUS AND THE LIKE 审中-公开
    本地互连网络(LIN)总线和类似设备接口的自适应静电放电(ESD)保护

    公开(公告)号:WO2009067672A3

    公开(公告)日:2009-07-09

    申请号:PCT/US2008084362

    申请日:2008-11-21

    CPC classification number: H01L27/0266 H02H9/046

    Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

    Abstract translation: 器件接口的自适应静电放电(ESD)保护在处理或安装到系统或从系统中移除时具有良好的ESD稳健性。 并且在系统中运行时,对DPI,电磁干扰(EMI)等具有强大的抗干扰能力。 在ESD保护金属氧化物半导体(MOS)器件的漏极和栅极之间存在显着的电容耦合,以在外部连接上没有(或低电平)DPI需要保护的情况下增强ESD保护并降低其回击电压 。 因此,当在外部连接上检测到显着的DPI / EMI信号时,MOS ESD保护装置的漏极和栅极之间的电容耦合被断开,旁路或衰减,从而增强了装置的DPI / EMI抗干扰性。

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