公开(公告)号：DE69934384D1

公开(公告)日：2007-01-25

申请号：DE69934384

申请日：1999-04-23

Applicant: MICROCHIP TECH INC

Inventor： ST AMAND ROGER ,  MA ROBERT ,  DEUTSCHER NEIL

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/314 ,  H01L21/32 ,  H01L21/76 ,  H01L27/08 ,  H01L29/78

Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

公开(公告)号：DE112019004131T5

公开(公告)日：2021-08-05

申请号：DE112019004131

申请日：2019-08-08

Applicant: MICROCHIP TECH INC

Inventor： DEUTSCHER NEIL ,  KRIS BRYAN

IPC: H03M1/60

Abstract: Ein Analog-Digital-Wandler (ADC) weist Spannungseingänge, einen Transkonduktor, der zum Umwandeln der Spannungseingänge in Ströme ausgebildet ist, stromgesteuerte Oszillatoren, einen Zähler und digitale Logik auf. Die stromgesteuerten Oszillatoren propagieren entsprechende Ströme vom Transkonduktor. Der Zähler ist so ausgebildet, dass er das wiederholte Durchlaufen eines oder mehrerer Oszillatoren zählt. Die digitale Logik ist so ausgebildet, dass sie basierend auf den Ergebnissen des Zählers einen Code bereitstellt, der ausgebildet ist, um einen Wert des zugehörigen Spannungseingangs anzugeben.

公开(公告)号：DE69934384T2

公开(公告)日：2007-09-27

申请号：DE69934384

申请日：1999-04-23

Applicant: MICROCHIP TECH INC

Inventor： ST AMAND ROGER ,  MA ROBERT ,  DEUTSCHER NEIL

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/314 ,  H01L21/32 ,  H01L21/76 ,  H01L27/08 ,  H01L29/78

Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

公开(公告)号：WO2010068873A2

公开(公告)日：2010-06-17

申请号：PCT/US2009067683

申请日：2009-12-11

Applicant: MICROCHIP TECH INC ,  DEUTSCHER NEIL ,  CHEN JINHUI ,  JONES MARQUIS

Inventor： DEUTSCHER NEIL ,  CHEN JINHUI ,  JONES MARQUIS

IPC: H03K3/356

CPC classification number: H03K3/356017 ,  H03K19/0016

Abstract: A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic "0" and one of the logic circuit modules is biased at a voltage level above the true ground, Vss, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic "0" to the true ground level. This eliminates sneak current and logic level corruption.

Abstract translation: 条件电平移位电路用于基本上消除在具有不同电压域中的两个或多个逻辑电路模块的集成电路装置中发生的潜行电流。 当不同电压域中的两个或多个逻辑电路模块之间的信号处于逻辑“0”时，引起潜行电流，并且逻辑电路模块中的一个偏置在高于集成电路器件的真实地Vss的电压电平 。 条件接地恢复电路将虚拟接地逻辑“0”移至真实的接地电平。 这消除了潜行和逻辑级别的破坏。