公开(公告)号：JP2001319487A

公开(公告)日：2001-11-16

申请号：JP2001083671

申请日：2001-03-22

Applicant: MICROCHIP TECH INC

Inventor： GERBER DONALD S ,  HEWITT KENT D ,  DAVIES DAVID M ,  SHELDS JEFFREY

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To provide an operation method for making the array of memory cells compact and compressing a memory cell densely. SOLUTION: This method is a method for operating memories including memory cells of the first and the second groups. The first group cells formed in a first semiconductor region are connected effectively to word lines and individual bit line, and the second group cells formed in a second semiconductor region are connected effectively to word lines and individual bit liens. This method includes a process applying first voltage to the word lines, a process applying second voltage to the first semiconductor region, a process applying selected voltage the bit lines of the first group cells, a process applying fourth voltage to the second semiconductor region, and a process applying fifth voltage to the bit lines of the second group cells.

公开(公告)号：AT337602T

公开(公告)日：2006-09-15

申请号：AT01106031

申请日：2001-03-12

Applicant: MICROCHIP TECH INC

Inventor： GERBER DONALD S ,  SHIELDS JEFFREY ,  HEWITT KENT D ,  DAVIES DAVID M

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

公开(公告)号：WO2010068674A3

公开(公告)日：2010-09-10

申请号：PCT/US2009067348

申请日：2009-12-09

Applicant: MICROCHIP TECH INC ,  SHIELDS JEFFREY A ,  HEWITT KENT D ,  GERBER DONALD S

Inventor： SHIELDS JEFFREY A ,  HEWITT KENT D ,  GERBER DONALD S

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/0416 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3427 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11803

Abstract: A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

Abstract translation: 一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。 此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。 多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

公开(公告)号：DE60122412T2

公开(公告)日：2007-05-03

申请号：DE60122412

申请日：2001-03-12

Applicant: MICROCHIP TECH INC

Inventor： GERBER DONALD S ,  SHIELDS JEFFREY ,  HEWITT KENT D ,  DAVIES DAVID M

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

公开(公告)号：DE60122412D1

公开(公告)日：2006-10-05

申请号：DE60122412

申请日：2001-03-12

Applicant: MICROCHIP TECH INC

Inventor： GERBER DONALD S ,  SHIELDS JEFFREY ,  HEWITT KENT D ,  DAVIES DAVID M

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.