MULTIPLE DEVICE INTEGRATED CIRCUIT PACKAGE WITH FEEDTHROUGH CONNECTION

    公开(公告)号:JPH11340415A

    公开(公告)日:1999-12-10

    申请号:JP11292099

    申请日:1999-04-20

    Abstract: PROBLEM TO BE SOLVED: To improve functionality of devices in a package by combining a first device with a second device, the second device having at least one feedthrough connector for coupling the first device to one of a plurality of pins via the second device. SOLUTION: A plurality of different devices 12 can be mounted on one lead frame 14 die paddle 16 construction without requiring an excessive bond wire length and bond angle i.e., without extending a bond wire on a second device 12B, while maintaining pin compatibility by an IC package 10. The IC package 10 enables this by providing a first device 12A coupled to one of a plurality of pins 20 via the second device 12B by a feedthrough connector 28 located on the second device 12B.

    SELF TIMED PRE-CHARGE SENSE AMPLIFIER

    公开(公告)号:JPH1186585A

    公开(公告)日:1999-03-30

    申请号:JP19795098

    申请日:1998-06-09

    Abstract: PROBLEM TO BE SOLVED: To improve high speed reading of a memory cell by providing a pre-charge device for rising a voltage level of a column of a memory array and connecting a state control circuit to monitor and control an output voltage of the pre-charge device. SOLUTION: Voltages in connecting points 44, 42 are in a grounding voltage when the input of an input terminal 40 is low, the output of a first NAND gate 48 is high, and a pre-charge transistor 54 is kept in an inactive state. An input voltage is risen, the pre-charge transistor 54 is activated, and the voltage an the connecting point 44 begins to rise toward VDD. When a transistor bias device 49 exists within a self timing pre-charge sense amplifier 30, the voltage in the connecting point 42 begins to rise toward VBIAS at the time point wherein the pre-charge transistor 54 becomes an active state. A sense amplifier 56 is connected for monitoring the output voltage, and the high speed reading is executed with the memory cell 32.

    3.
    发明专利
    未知

    公开(公告)号:ES2132049T1

    公开(公告)日:1999-08-16

    申请号:ES97926507

    申请日:1997-05-21

    Abstract: The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external components. The microcontroller can function in a proper manner from the application of only power and signal lines with no external components required. The microcontroller has integrated internal reset and oscillator circuitry into the microcontroller. The microcontroller has also integrated simple external components such as current limiting resistors and pull up and pull down resistor into the microcontroller in order to avoid application specific external components.

    WÄHLBARE EINGABEPUFFER VON ALLZWECK-EINGÄNGEN UND MIKROCONTROLLER MIT DENSELBEN

    公开(公告)号:DE112020003106T5

    公开(公告)日:2022-04-21

    申请号:DE112020003106

    申请日:2020-06-24

    Abstract: Eine oder mehrere Ausführungsformen beziehen sich im Allgemeinen auf den Mikrocontroller-Eingang/Ausgang (E/A) und die Begrenzung oder Deaktivierung der statischen Stromaufnahme an Allzweck-Eingängen, einschließlich in Situationen mit niedriger Leistung, in denen eine Eingangsspannung niedriger als eine Versorgungsspannung sein kann. In einigen Ausführungsformen kann ein Allzweck-Eingang wählbare Eingangspuffer und eine Logik einschließen, die so konfiguriert ist, dass sie einen Eingangspuffer, der einem Spannungsbereich zugeordnet ist, der im Wesentlichen mit einer Eingangsspannung des Allzweck-Eingangs übereinstimmt, selektiv aktiviert und die anderen Eingangspuffer selektiv deaktiviert.

    POWER-ON RESET CIRCUIT
    7.
    发明公开
    POWER-ON RESET CIRCUIT 失效
    快速上电复位电路

    公开(公告)号:EP0787379A4

    公开(公告)日:1999-08-25

    申请号:EP96924422

    申请日:1996-07-17

    CPC classification number: H03K17/223 G11C5/143 H02H3/243 H03K17/145 H03K17/22

    Abstract: A power-on reset circuit (10) for resetting electronic circuitry to be monitored has been provided. The power-on reset circuit includes a trip point generator (12) including the worst case component (the component that requires the greatest power supply voltage to operate) within the electronic circuitry for setting the threshold voltatge for taking the electronic circuitry out of reset such that if the worst case component is operative, it is guaranteed that all components are operative and, thus, the electronic circuitry can be taken out of reset. Moreover, because the threshold voltage is based upon the worst case component of the electronic circuitry, the threshold voltage of the trip point generator will adequately track the electronic circuitry over normal process and temperature variations. Additionally, the power-on reset circuit includes a noise filter (34) for placing the electronic circuitry back into reset if variations within the power supply voltage cause the power supply voltage level to fall below a predetermined threshold for at least a minimum period of time.

    HIGH VOLTAGE LEVEL SHIFTING CMOS BUFFER
    8.
    发明公开
    HIGH VOLTAGE LEVEL SHIFTING CMOS BUFFER 失效
    CMOS-PEGELSCHIEBEPUFFERFÜRHOHE SPANNUNGEN

    公开(公告)号:EP0864203A4

    公开(公告)日:2001-02-07

    申请号:EP97943473

    申请日:1997-09-25

    CPC classification number: H03K3/356113 H03K17/102

    Abstract: A voltage level shifting complementary metal-oxide-silicon (CMOS) buffer (30-47) is arranged and configured to operate in two distinct modes - one of which is high voltage and the other low voltage - depending on the level of the supply voltage (40) to the buffer relative to the operating voltage (VDD) of a device in which the buffer is integrated. In the high voltage mode, in which the supply voltage level exceeds the operating voltage level, the buffer is constrained to perform as a high voltage level shifter. In the low voltage mode, in which the supply voltage level is equal to or less than the operating voltage level, the buffer is constrained to perform as a CMOS logic gate.

    Abstract translation: 互补金属氧化物硅(CMOS)缓冲器(30-47)的电压电平移位被配置和配置为以两种不同的模式操作 - 其中一种是高电压,另一种是低电压 - 取决于电源电压 (40)相对于其中集成缓冲器的装置的工作电压(VDD)到缓冲器。 在电源电压超过工作电压电平的高电压模式下,缓冲器被限制为高电压电平移位器。 在电源电压等于或小于工作电压电平的低电压模式中,缓冲器被限制为执行CMOS逻辑门。

    OVERCHARGE/DISCHARGE VOLTAGE REGULATOR FOR EPROM MEMORY ARRAY
    9.
    发明公开
    OVERCHARGE/DISCHARGE VOLTAGE REGULATOR FOR EPROM MEMORY ARRAY 失效
    过充/放电电压调节器的EPROM存储器区

    公开(公告)号:EP0864154A4

    公开(公告)日:2000-06-14

    申请号:EP97943474

    申请日:1997-09-25

    CPC classification number: G11C16/26

    Abstract: A method of high speed reading of data from an EPROM, in which a memory array (12) is programmed based on device status at intersections of rows and columns of the array to store data therein as 0's and 1's, uses a capacitive overcharging and discharging technique to enable fast voltage stabilization without drawing significant current. A row containing memory element (25) to be read is quickly overdriven to overcharge an effective capacitance associated with the row to substantially the maximum level of the EPROM supply voltage (Vdd) which may exceed the programmed threshold voltage of the selected memory element (25). The effective capacitance is thereupon discharged to voltage level below both the maximum level of the supply voltage (Vdd) and the programmed threshold. Then the status and data content of the selected memory element (25) are read by first grounding an electrode of a source-drain path of the transistor comprising the memory element (25) to cause current with substantially no DC component to flow through that path of the transistor. A sense amplifier (17) in source-drain path of the transistor is triggered to detect current flow therethrough as indicative of the data content of the memory element (25).

    MICROCONTROLLER WITH FIRMWARE SELECTABLE OSCILLATOR TRIMMING
    10.
    发明公开
    MICROCONTROLLER WITH FIRMWARE SELECTABLE OSCILLATOR TRIMMING 失效
    MIKROCONTROLLER MIT系统ZUMFIRMWAREAUSWÄHLBARENTRIMMEN EINES OSZILLATORS

    公开(公告)号:EP0840955A4

    公开(公告)日:1998-12-23

    申请号:EP97926506

    申请日:1997-05-21

    Abstract: A microcontroller circuit having firmware selectable oscillator trimming includes, in combination, a microcontroller, an oscillator located within the microcontroller for providing a system clock signal for the microcontroller, and a memory portion for providing trimming data to the oscillator for trimming frequency of the system clock. The microcontroller circuit includes microcontroller logic which has the trimming data stored therein for transfer to the memory portion. Additionally, the microcontroller logic permits the user to alter the trimming data after it has been transferred to the memory portion, thereby permitting the user to alter the amount of modification of the system clock frequency from the amount associated with the trimming data.

    Abstract translation: 微控制器电路(10)包括在微控制器逻辑(12)的控制下从存储器(16)接收频率调整数据(28)的振荡器(14)。 微控制器逻辑(12)允许用户改变调整数据并通过振荡器逻辑(20)选择振荡器(14)或外部振荡器源(34)作为系统时钟(32)。

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