公开(公告)号：JPH11232100A

公开(公告)日：1999-08-27

申请号：JP30756298

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  JOHANSEN DARREL ,  YACH RANDY L ,  BOLES BRIAN

IPC: G06F9/35

Abstract: PROBLEM TO BE SOLVED: To generate an indirect addressing mode address by providing a multiplexer circuit connected to the respective output terminals of a data pointer register, an incrementer and an adder. SOLUTION: A data pointer register 12 stores the current address of an operand used in a simple indirect addressing mode. An incrementer 14 increases the current address of the operand stored in the data pointer register 12. An adder 16 adds the current address and an offset value stored in the data pointer register 12. A multiplexer circuit 18 having a first input terminal connected to the output terminal of the data pointer register 12, a second input terminal connected to the output terminal of the incrementer 14 and a third input terminal connected to the output terminal of the adder 16 selects a desired generated indirect addressing mode address and outputs the selected address to an instruction register.

公开(公告)号：JPH11224192A

公开(公告)日：1999-08-17

申请号：JP30756098

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  YACH RANDY L ,  TRIECE JOSEPH W ,  CHIAO JENNIFER ,  WOJEWODA IGOR ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To increase a memory base capable of addressing by providing a second address bus for supplying all the address values of a two-word instruction to a linearized program memory in one cycle. SOLUTION: A first address bus 14 is connected to the linearized program memory 12 and is used for sending the address of a fetched instruction to the linearized program memory 12. A pointer 16 is connected to the first address bus 14. The second address bus 20 is provided with a first end part connected to the output of the linearized program memory 12 and the second end part of the second address bus 20 is connected to the first address bus 14. The second address bus 20 is used for arranging the address of the operand of the second word (word fetched during the execution of a first word) of the two-word instruction on the first address bus 14 after the address of the operand of the first word of the two-word instruction is arranged on the first address bus 14.

公开(公告)号：JP2001249845A

公开(公告)日：2001-09-14

申请号：JP2001044208

申请日：2001-02-20

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  H02J13/00

Abstract: PROBLEM TO BE SOLVED: To provide improved microcontroller structure and a paging system not to increase the size of a microcontroller. SOLUTION: This paging system includes a process to linearize the entire address area of a random access memory, a process to divide the linearized address area of the random access memory into plural pages and in which each of the plural pages is selected from a group with size of 256 bytes and 64 K bytes, a process to use the pages of the random access memory exclusive for special and multi-purpose registers and a process not to affect the present operation of the microcomputer and not to change the presently selected address stored in a page selection register which is used by the microcomputer when the microcomputer is set so that forced data access is generated by the exclusive pages.

公开(公告)号：JPH1186585A

公开(公告)日：1999-03-30

申请号：JP19795098

申请日：1998-06-09

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L ,  HULL RICHARD L

IPC: G11C16/02 ,  G11C7/06 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To improve high speed reading of a memory cell by providing a pre-charge device for rising a voltage level of a column of a memory array and connecting a state control circuit to monitor and control an output voltage of the pre-charge device. SOLUTION: Voltages in connecting points 44, 42 are in a grounding voltage when the input of an input terminal 40 is low, the output of a first NAND gate 48 is high, and a pre-charge transistor 54 is kept in an inactive state. An input voltage is risen, the pre-charge transistor 54 is activated, and the voltage an the connecting point 44 begins to rise toward VDD. When a transistor bias device 49 exists within a self timing pre-charge sense amplifier 30, the voltage in the connecting point 42 begins to rise toward VBIAS at the time point wherein the pre-charge transistor 54 becomes an active state. A sense amplifier 56 is connected for monitoring the output voltage, and the high speed reading is executed with the memory cell 32.

公开(公告)号：JP2002189537A

公开(公告)日：2002-07-05

申请号：JP2001276540

申请日：2001-09-12

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L

IPC: G01R19/165 ,  G06F1/24 ,  G06F1/28 ,  G06F1/30 ,  G06F11/30 ,  G06F15/78 ,  H02H3/247

Abstract: PROBLEM TO BE SOLVED: To provide a blown-out detection circuit capable of analyzing the features of power supply voltage dip, and collating it with a prescribed reference and hysteresis, and deciding whether or not reset should be started each time the power supply voltage is made less than a threshold level. SOLUTION: A microcontroller device controls an external system set on the same circuit as that of the device. A microcontroller is provided with a CPU 10, a program memory 12, a data memory 13, and various peripheral elements. A blown-out protection circuit 16 monitors the power supply voltage level for a chip, and when the difference between the power supply voltage and a ground reference level becomes less than a threshold operating voltage level, resets the device, and operates so that the malfunction of the device can be prevented. The operation of the device is stopped when reset while status of implementation of a program instruction by the CPU 10 and data stored in the data memory 13 are maintained as they are when the device is reset.

公开(公告)号：JPH11149372A

公开(公告)日：1999-06-02

申请号：JP22514098

申请日：1998-07-03

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F12/02 ,  G06F12/06 ,  H02J13/00

Abstract: PROBLEM TO BE SOLVED: To add an exclusive bit to an operation code decoding column and to force data access generated in the page '0' of a random access memory(RAM) for an instruction. SOLUTION: A user can select an arbitrary page and can directly access to a specified function register positioned in the page '0' of RAM 22 or to a register variable. Setting of an exclusive bit does not affect present operation of a micro controller 20, or setting of the bit does not correct and address which is stored in an operation code instruction executed at present by the micro controller and is selected at present.

公开(公告)号：AU9111901A

公开(公告)日：2002-04-02

申请号：AU9111901

申请日：2001-09-20

Applicant: MICROCHIP TECH INC

Inventor： HULL RICHARD L ,  YACH RANDY L ,  HEWITT KENT D

IPC: H03F3/30 ,  H03K19/0185 ,  H03K19/096

公开(公告)号：DE69231230D1

公开(公告)日：2000-08-10

申请号：DE69231230

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L ,  MITRA SUMIT

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/267 ,  G06F15/78 ,  G06F11/00 ,  G06F1/00 ,  G06F9/00 ,  H03K17/22 ,  H03K17/28

Abstract: A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condition is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.

公开(公告)号：ES2165651T3

公开(公告)日：2002-03-16

申请号：ES98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE69801355D1

公开(公告)日：2001-09-20

申请号：DE69801355

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.