公开(公告)号：EP1393166A1

公开(公告)日：2004-03-03

申请号：EP02752011.3

申请日：2002-05-30

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael ,  TRIECE, Joseph, W. ,  PYSKA, Michael ,  CONNER, Joshua, M.

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/345 ,  G06F9/30 ,  G06F12/10

CPC classification number: G06F9/342 ,  G06F9/30185 ,  G06F9/345 ,  G06F12/0284 ,  G06F12/109

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

公开(公告)号：EP1393183A1

公开(公告)日：2004-03-03

申请号：EP02734553.7

申请日：2002-05-29

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael

IPC: G06F12/00 ,  G06F12/14 ,  G06F11/00

CPC classification number: G06F9/3802 ,  G06F9/3861 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1416

Abstract: A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space.

公开(公告)号：EP1393166B1

公开(公告)日：2011-08-17

申请号：EP02752011.3

申请日：2002-05-30

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael ,  TRIECE, Joseph, W. ,  PYSKA, Michael ,  CONNER, Joshua, M.

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/345 ,  G06F9/30 ,  G06F12/10

CPC classification number: G06F9/342 ,  G06F9/30185 ,  G06F9/345 ,  G06F12/0284 ,  G06F12/109

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

公开(公告)号：EP1393183B1

公开(公告)日：2007-09-12

申请号：EP02734553.7

申请日：2002-05-29

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael

IPC: G06F12/00 ,  G06F12/14 ,  G06F11/00

CPC classification number: G06F9/3802 ,  G06F9/3861 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1416

Abstract: A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space.

公开(公告)号：EP1393163A1

公开(公告)日：2004-03-03

申请号：EP02739496.4

申请日：2002-05-31

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael ,  BOLES, Brian ,  BOWLING, Stephen, A. ,  CONNER, Joshua, M. ,  DRAKE, Rodney ,  TRIECE, Joseph, W. ,  ELLIOT, John ,  FALL, Brian, Neil ,  GROSBACH, James, H. ,  KUHRT, Tracy, Ann ,  McCARTHY, Guy ,  MURO, Manuel, Jr. ,  PYSKA, Michael

IPC: G06F9/30 ,  G06F9/38 ,  G09F9/302

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/3893

Abstract: An instruction set is provided that features ninety four instructions and various address modes to deliver a mixture of flexible micro-controller like instructions and specialized digital signal processor (DSP) instructions that execute from a single instruction stream.