公开(公告)号：EP1706817A1

公开(公告)日：2006-10-04

申请号：EP04795502.6

申请日：2004-10-18

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BOLES, Edward, Brian ,  DRAKE, Rodney, Jay ,  JOHANSEN, Darrel, Ray ,  MITRA, Sumit, K. ,  YACH, Randy ,  GROSBACH, James ,  CONNER, Joshua, M. ,  TRIECE, Joseph, W.

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30167 ,  G06F9/35

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

公开(公告)号：EP1086466A1

公开(公告)日：2001-03-28

申请号：EP00917817.9

申请日：2000-03-09

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： WOJEWODA, Igor ,  TRIECE, Joseph, W.

IPC: G11C16/22 ,  G11C29/00 ,  G06F1/22

CPC classification number: G11C16/225 ,  G06F9/24 ,  G06F9/30101 ,  G11C16/22

Abstract: A microcontroller having a memory programmable in user mode. The microcontroller contains circuitry for detecting whether a programming level voltage has been activated. Also included is a Longwrite enable register containing an enable bit for enabling/disabling programming of the memory. When the register contains the bit indicating programming as enabled, and the programming level voltage is detected, the microcontroller allows the program memory to be programmed. The programming can take place in user mode. The programming level voltage signal is also used to detect whether to enter into a test mode. Programming of the program memory is also possible in the test mode. The invention is also directed to a method for operating a microcontroller for controlling programming of the program memory. The microcontroller according to the invention allows increased functionality by detecting whether to enter the test mode without the requirement of a test mode select input signal.

公开(公告)号：EP1393166A1

公开(公告)日：2004-03-03

申请号：EP02752011.3

申请日：2002-05-30

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael ,  TRIECE, Joseph, W. ,  PYSKA, Michael ,  CONNER, Joshua, M.

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/345 ,  G06F9/30 ,  G06F12/10

CPC classification number: G06F9/342 ,  G06F9/30185 ,  G06F9/345 ,  G06F12/0284 ,  G06F12/109

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

公开(公告)号：EP1706817B1

公开(公告)日：2015-04-15

申请号：EP04795502.6

申请日：2004-10-18

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BOLES, Edward, Brian ,  DRAKE, Rodney, Jay ,  JOHANSEN, Darrel, Ray ,  MITRA, Sumit, K. ,  YACH, Randy ,  GROSBACH, James ,  CONNER, Joshua, M. ,  TRIECE, Joseph, W.

IPC: G06F9/30 ,  G06F9/35

CPC classification number: G06F9/30145 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30167 ,  G06F9/35

公开(公告)号：EP1393166B1

公开(公告)日：2011-08-17

申请号：EP02752011.3

申请日：2002-05-30

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael ,  TRIECE, Joseph, W. ,  PYSKA, Michael ,  CONNER, Joshua, M.

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/345 ,  G06F9/30 ,  G06F12/10

CPC classification number: G06F9/342 ,  G06F9/30185 ,  G06F9/345 ,  G06F12/0284 ,  G06F12/109

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

公开(公告)号：EP1393163A1

公开(公告)日：2004-03-03

申请号：EP02739496.4

申请日：2002-05-31

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： CATHERWOOD, Michael ,  BOLES, Brian ,  BOWLING, Stephen, A. ,  CONNER, Joshua, M. ,  DRAKE, Rodney ,  TRIECE, Joseph, W. ,  ELLIOT, John ,  FALL, Brian, Neil ,  GROSBACH, James, H. ,  KUHRT, Tracy, Ann ,  McCARTHY, Guy ,  MURO, Manuel, Jr. ,  PYSKA, Michael

IPC: G06F9/30 ,  G06F9/38 ,  G09F9/302

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/3893

Abstract: An instruction set is provided that features ninety four instructions and various address modes to deliver a mixture of flexible micro-controller like instructions and specialized digital signal processor (DSP) instructions that execute from a single instruction stream.