公开(公告)号：MY173261A

公开(公告)日：2020-01-09

申请号：MYUI20072075

申请日：2007-11-22

Applicant: MIMOS BERHAD

Inventor： KHAIRIL MAZWAN MOHD ZAINI ,  WAN IDRUS ,  ANIFAH ZAKARIA

Abstract: A method for removing photoresist using Wafer Edge Exclusion (WEE) from the water coding area is disclosed herein. WEE is used at metal-1 layer and metal-2 layers in order to reduce the topographical defects around the water coding area. Figure 2

公开(公告)号：MY180765A

公开(公告)日：2020-12-08

申请号：MYPI2012002621

申请日：2012-06-11

Applicant: MIMOS BERHAD

Inventor： ANIFAH ZAKARIA ,  MOHD HEZRI ABU BAKAR ,  FADZILAH ARIFIN ,  MOHD HILMY AZUAN HAMZAH

Abstract: A method of fabrication of an oxide layer at the bottom of a trench in a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is provided. The method includes deposition of a pad oxide layer on a semiconductor substrate of the MOSFET (102); etching the pad oxide layer and the semiconductor substrate to form a trench in the semiconductor substrate(104); depositing a silicone oxide layer to fill the trench in the semiconductor substrate (108); etching the silicone oxide layer to remove the silicone oxide layer from a plurality of sidewalls of the trench (110); coating the semiconductor substrate and silicone oxide layer with a photoresist to protect them of etching (112); etching the photoresist and the silicone oxide layer until surface of the semiconductor substrate is reached (114); and removing the photoresist from inside the trench to obtain a thick bottom oxide (TBO) layer in the trench.

公开(公告)号：MY172637A

公开(公告)日：2019-12-06

申请号：MYUI2014703023

申请日：2014-10-14

Applicant: MIMOS BERHAD

Inventor： KHAIRIL MAZWAN MOHD ZAINI ,  NAZRAH OMAR ,  ANIFAH ZAKARIA

Abstract: The present invention provides a design of overlay feature for wafer fabrication. The design pattern is overlay featuring first via [20] and second via [24] reticles with smaller via boxes instead of one big via box. This way, during application procedures residues can be eliminated after tungsten plug process ensuring new and clean box in box pattern instead of deformed box in box. This overlay feature consist of a four line series of via, via boxes of nine units or more in a line, to eliminate residue after tungsten plug process. This overlay feature consist of a set of four line series of via forming part of a hypothetical square as a replacement of one big square via hole. This design improves the overlay feature and helps overcome overlay measurement problems. As such, improvement in accuracy of data measurement provides correct alignments results which enable alignment correction and thus ensure higher production yield. This design solves the overlay problem and can be placed at any via masks (first via [20] and second via [22]) of new products, replacing standard overlay box-box feature without any changes in process recipes of standard CMOS wafer fabrication.