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公开(公告)号：BR9105891A
公开(公告)日：1992-10-13
申请号：BR9105891
申请日：1991-07-29
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER , RABE DUANE C
Abstract: A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of each accumulator are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.
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公开(公告)号：DE69121040T2
公开(公告)日：1997-02-20
申请号：DE69121040
申请日：1991-04-22
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER , RABE DUANE
Abstract: A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
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公开(公告)号：DE69121040D1
公开(公告)日：1996-08-29
申请号：DE69121040
申请日：1991-04-22
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER , RABE DUANE
Abstract: A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
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公开(公告)号：SE9401053D0
公开(公告)日：1994-03-29
申请号：SE9401053
申请日：1994-03-29
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER , STOCKSTAD TROY L , VYNE ROBERT L
Abstract: A TC controlled RF signal detecting circuitry (211) used in the output power control circuit of a TDMA RF signal power amplifier includes positive coefficient current source (303) producing current I+ having a positive TC, negative coefficient current source (305) producing current I- having a negative TC, and current mirror (301) for summing currents I+ and I- to produce substantially identical compensated mirror currents Im1 and Im2. Anti-clamping current mirror (309) mirrors current Im2 to produce compensated currents Ia1 and Ia2, which are applied to and bias a Schottky diode coupled in series to a resistor network in each leg of diode detector (311). Each leg of diode detector (311) has a positive TC, which is substantially offset by the negative TC of compensated currents Ia1 and Ia2. Schottky diode (431) in one leg of diode detector (311) half-wave rectifies RF feedback signal (212) to produce temperature and voltage compensated power level signal (229), which has a DC level proportional to the output power level of RF output signal (214). By using TC controlled RF signal detecting circuitry (211), power level signal (229) has a DC level which is stable to within 5 mV over temperature ranging from -55 DEG C. to +125 DEG C. and over power supply voltage ranging from 2.7 V to 4.75 V.
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