公开(公告)号：WO1995013664A1

公开(公告)日：1995-05-18

申请号：PCT/US1994011766

申请日：1994-10-17

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  CONNELL, Lawrence, Edwin ,  CALLICOTTE, Mark, Joseph ,  HADDAD, Kenneth, Robert

IPC: H04B01/04

CPC classification number: H03H19/004

Abstract: A method and apparatus integrate a plurality of input signals. A first integrator (225) integrates a first of the input signals and a second integrator (230) integrates a second of the input signals. A summer (235) is connected to the first and second integrators to then sum the integrated first and second signals and provide a composite integrated signal.

Abstract translation: 集成多个输入信号的方法和装置。 第一积分器（225）积分第一输入信号，第二积分器（230）对第二输入信号进行积分。 夏季（235）连接到第一和第二积分器，然后对积分的第一和第二信号求和，并提供复合积分信号。

公开(公告)号：WO1990001833A1

公开(公告)日：1990-02-22

申请号：PCT/US1989002630

申请日：1989-06-16

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  CONNELL, Lawrence, Edwin ,  LICHTSCHEIDL, Gregg, Richard

IPC: H03L05/00

CPC classification number: H03K19/018521 ,  H03K12/00

Abstract: A low current CMOS translator arrangement is disclosed that utilizes a low current inverting stage (302), having a peak current requirement, fed by a constant current source (304) at a supply node that also has a capacitor coupled to it (306). This low current inverter is useful for a number of applications, including generating a sinusoidal signal when it is coupled to a crystal. When one or more are cascaded and coupled to a square wave input signal, the arrangement becomes a low current translator that level-shifts, or translates, the input signal having a first voltage range to a translated square wave output signal having a second voltage range.

公开(公告)号：EP0759198A1

公开(公告)日：1997-02-26

申请号：EP95944681.0

申请日：1995-12-28

Applicant: MOTOROLA, INC.

Inventor： CONNELL, Lawrence, Edwin ,  HOLOUBEK, Kevin, Joseph

IPC: G06F7 ,  G06F17 ,  H03H17

CPC classification number: H03H17/0263 ,  G06F17/18

Abstract: An efficient method and apparatus of median filtering includes a memory circuit (305) for holding a list of N data samples (109). A grading circuit (309, 321, 313, 311) identifies a first data sample of the N data samples that has a first metric with a magnitude less than or equal to (N-1)/2, and a second metric with a magnitude greater than or equal to (N-1)/2. The first metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than a magnitude of the first data sample. The second metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than or equal to the magnitude of the first data sample.

公开(公告)号：WO1996027830A1

公开(公告)日：1996-09-12

申请号：PCT/US1995017017

申请日：1995-12-28

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  CONNELL, Lawrence, Edwin ,  HOLOUBEK, Kevin, Joseph

IPC: G06F07/00

CPC classification number: H03H17/0263 ,  G06F17/18

Abstract: An efficient method and apparatus of median filtering includes a memory circuit (305) for holding a list of N data samples (109). A grading circuit (309, 321, 313, 311) identifies a first data sample of the N data samples that has a first metric with a magnitude less than or equal to (N-1)/2, and a second metric with a magnitude greater than or equal to (N-1)/2. The first metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than a magnitude of the first data sample. The second metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than or equal to the magnitude of the first data sample.

Abstract translation: 中值滤波的有效方法和装置包括用于保存N个数据采样列表（109）的存储器电路（305）。 分级电路（309,321,313,311）识别具有幅度小于或等于（N-1）/ 2的第一度量的N个数据采样的第一数据采样，以及具有幅度的第二度量 大于或等于（N-1）/ 2。 第一度量表示除了第一数据样本之外的具有小于第一数据样本量值的数据量的数据样本数量。 第二度量指示具有小于或等于第一数据样本的幅度的幅度的数据样本量，排除第一数据样本。

公开(公告)号：WO1996018243A1

公开(公告)日：1996-06-13

申请号：PCT/US1995013867

申请日：1995-10-27

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  CONNELL, Lawrence, Edwin ,  KANG, David, Dukho ,  HOLLENBECK, Neal, Wayne ,  ROECKNER, William, J.

IPC: H04B01/10

CPC classification number: H04L7/0054 ,  G06J1/00 ,  H03M1/1009 ,  H04L7/033 ,  H04L7/0334

Abstract: An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

Abstract translation: 干扰相关自适应相位时钟控制器方法和系统包括信号处理时钟信号的合成（307）。 测量依赖于信号处理时钟信号的相位的干扰信号（311），并依赖于相位校正信号（317）。 通过根据相位校正信号（317）调整信号处理时钟信号（307）的相位来减小干扰信号的大小。

公开(公告)号：WO2003021768A1

公开(公告)日：2003-03-13

申请号：PCT/US2002/027787

申请日：2002-09-03

Applicant: MOTOROLA, INC.

Inventor： HOLLENBECK, Neal, W. ,  CONNELL, Lawrence, Edwin

IPC: H03F3/04

CPC classification number: H03F3/193

Abstract: A single ended input differential output amplifier (100) and integrated circuit including an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between RFIN and a source bias voltage VBS. A first field effect transistor (FET) (108) is connected between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage, VBg, is connected to FET (108) through resistor (112) to FET (110). A coupling capacitor (114) is connected between the input RFIN and FET (110). FET (108) may be connected to gate bias voltage VBg through a second gate bias resistor (122).

Abstract translation: 单端输入差分输出放大器（100）和包括放大器（100）的集成电路。 一对负载电阻（102,104）连接在电源电压（Vdd）和差分输出OUTP和OUTM之间。 电感器（106）连接在RFIN和源极偏置电压VBS之间。 第一场效应晶体管（FET）（108）连接在RFIN处的输出OUTP的负载电阻（102）和电感（106）之间。 第二FET（110）在输出OUTM处连接在第二负载电阻（104）和源极偏置电压VBS之间。 栅极偏置电压VBg通过电阻（112）连接到FET（108）至FET（110）。 耦合电容器（114）连接在输入RFIN和FET（110）之间。 FET（108）可以通过第二栅极偏置电阻（122）连接到栅极偏置电压VBg。

公开(公告)号：WO1989012351A1

公开(公告)日：1989-12-14

申请号：PCT/US1989001832

申请日：1989-05-01

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  CONNELL, Lawrence, Edwin

IPC: H03B05/36

CPC classification number: H03B5/368 ,  H03B2200/0008 ,  H03B2200/0012 ,  H03B2200/004 ,  H03B2200/005 ,  H03B2201/0208 ,  H03B2201/0283 ,  H03J2200/10

Abstract: A fully integrated, adjustable oscillator circuit for use with a crystal is disclosed in which a crystal oscillator, such as a Pierce oscillator, is arranged to utilize a tuning network that includes at least one integrated varactor (voltage-variable-capacitor) as a shunt element for providing at least one type of adjustment of the oscillating signal. More than one type of adjustment can be provided by including a bank of varactors for each of the shunt elements of the tuning network, in which various individual varactors are selected in binary (on-off) fashion to effect digital as well as analog adjustment of the crystal oscillator.

公开(公告)号：WO1996036886A1

公开(公告)日：1996-11-21

申请号：PCT/US1996004585

申请日：1996-04-11

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  CONNELL, Lawrence, Edwin

IPC: G01R31/28

CPC classification number: G01R31/318558

Abstract: An addressable serial test system employs a serial register with parallel outputs (103). Data is clocked into the serial register via a shift clock signal (105). A decoder (107, 109) is connected to a portion of the shift register's outpus (101) and provides a selection signal (111) dependent on the data clocked into the serial register. A system clock generates a system clock signal (112). A storage element (A-P) includes a clock input (C) coupled to the system clock signal, a data input (D), an output (Q), a load input coupled to the selection signal (LD), and a test data input (TI) coupled to another portion of the shift register's outputs (100). The storage element's output is alternately forced to a state indicative of the test data input by the selection signal and forced to a state indicative of the data input by the system clock. Structure is included to configure the serial register to read the contents of the storage element.

Abstract translation: 可寻址串行测试系统采用具有并行输出的串行寄存器（103）。 数据通过移位时钟信号（105）被输入到串行寄存器中。 解码器（107,109）连接到移位寄存器的out us（101）的一部分，并提供取决于计时到串行寄存器中的数据的选择信号（111）。 系统时钟产生系统时钟信号（112）。 存储元件（AP）包括耦合到系统时钟信号的时钟输入（C），数据输入（D），输出（Q），耦合到选择信号（LD）的负载输入和测试数据输入 （TI）耦合到移位寄存器的输出（100）的另一部分。 存储元件的输出被交替地强制为指示由选择信号输入的测试数据的状态，并被强制为指示由系统时钟输入的数据的状态。 包括结构以配置串行寄存器来读取存储元件的内容。

公开(公告)号：WO1995013655A1

公开(公告)日：1995-05-18

申请号：PCT/US1994011764

申请日：1994-10-17

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  CONNELL, Lawrence, Edwin ,  CALLICOTTE, Mark, Joseph ,  ROECKNER, William, Joseph

IPC: H03G07/00

CPC classification number: H03G7/007

Abstract: A level detector detects an input signal lever (205). A rectifier (210) receives the input signal and provides a rectified signal (215). A prefilter (220) receives the rectified signal and attenuates high frequency components at frequencies near multiples of a decimation sample rate. The prefilter signal (225) is decimitated by a decimator (230) and low pass filtered by a low pass filter (240) having a passband below the input frequency of the input signal. The level detector can be provided to control a variable gain stage circuit which applies a gain to the input signal based on the level to form a dynamic range compressor or expander.

Abstract translation: 电平检测器检测输入信号杆（205）。 整流器（210）接收输入信号并提供整流信号（215）。 预滤波器（220）接收经整流的信号，并以接近抽取采样率的倍数的频率衰减高频分量。 预滤波器信号（225）由抽取器（230）分频，并且通过具有低于输入信号的输入频率的通带的低通滤波器（240）进行低通滤波。 可以提供电平检测器来控制可变增益级电路，该可变增益级电路基于电平对输入信号施加增益以形成动态范围压缩器或扩展器。

公开(公告)号：EP0776481B1

公开(公告)日：2003-08-20

申请号：EP96912552.5

申请日：1996-04-11

Applicant: MOTOROLA, INC.

Inventor： CONNELL, Lawrence, Edwin

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318558

Abstract: An addressable serial test system employs a serial register with parallel outputs (103). Data is clocked into the serial register via a shift clock signal (105). A decoder (107, 109) is connected to a portion of the shift register's outpus (101) and provides a selection signal (111) dependent on the data clocked into the serial register. A system clock generates a system clock signal (112). A storage element (A-P) includes a clock input (C) coupled to the system clock signal, a data input (D), an output (Q), a load input coupled to the selection signal (LD), and a test data input (TI) coupled to another portion of the shift register's outputs (100). The storage element's output is alternately forced to a state indicative of the test data input by the selection signal and forced to a state indicative of the data input by the system clock. Structure is included to configure the serial register to read the contents of the storage element.