CALIBRACION DE MEMORIA ADAPTABLE USANDO CONTENEDORES.

    公开(公告)号:ES2326903T3

    公开(公告)日:2009-10-21

    申请号:ES05817276

    申请日:2005-11-07

    Applicant: QUALCOMM INC

    Abstract: Un procedimiento de calibración de un circuito integrado para un componente electrónico, el circuito integrado teniendo un reloj de sistema, comprendiendo el procedimiento: generar un reloj externo en el circuito integrado, teniendo el reloj externo un retardo programable respecto del reloj de sistema; proporcionar un reloj externo a partir del circuito integrado al componente electrónico para soportar las comunicaciones con el mismo; caracterizado por los pasos de determinar (600) un intervalo de retardo entre el reloj de sistema y el reloj externo en el que el circuito integrado y el componente electrónico puedan comunicar; y programar (700) el reloj externo con una de una pluralidad de valores de retardo predeterminados en base al intervalo de retardo.

    2.
    发明专利
    未知

    公开(公告)号:AT430320T

    公开(公告)日:2009-05-15

    申请号:AT05817276

    申请日:2005-11-07

    Applicant: QUALCOMM INC

    Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

    INTEGRATED CIRCUIT WITH ADAPTIVE SPEED BINNING

    公开(公告)号:CA2586445A1

    公开(公告)日:2006-05-18

    申请号:CA2586445

    申请日:2005-11-04

    Applicant: QUALCOMM INC

    Abstract: Systems and techniques are disclosed relating to adapting the frequency of an electronic device comprising an integrated circuit and an electronic component to improve performance. The integrated circuit determines a set of frequency plans, each corresponding to a distribution of delay range highest passing values and one of a set of frequencies at which the electronic device can operate. Based on communication with the electronic component, the integrated circuit implements a preferred frequency plan.

    4.
    发明专利
    未知

    公开(公告)号:DE602005014264D1

    公开(公告)日:2009-06-10

    申请号:DE602005014264

    申请日:2005-11-07

    Applicant: QUALCOMM INC

    Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

    CALIBRACION DE MEMORIA ADAPTIVA UTILIZANDO DEPOSITOS.

    公开(公告)号:MX2007005484A

    公开(公告)日:2007-07-16

    申请号:MX2007005484

    申请日:2005-11-07

    Applicant: QUALCOMM INC

    Abstract: Un dispositivo electronico comprende un componente electronico y un circuito integrado, en donde el circuito integrado esta configurado para generar un reloj de sistema y un reloj externo que tiene un retraso programable a partir del reloj del sistema, proveer el reloj externo al componente electronico, determinar un rango de retraso entre el reloj del sistema y el reloj externo en donde el circuito integrado y el componente electronico pueden establecer comunicacion, y programar el reloj externo con uno de una pluralidad de valores de retraso predeterminados con base en el rango de retraso.

    6.
    发明专利
    未知

    公开(公告)号:BRPI0416892A

    公开(公告)日:2007-03-06

    申请号:BRPI0416892

    申请日:2004-11-24

    Applicant: QUALCOMM INC

    Abstract: Systems and techniques are disclosed relating to calibrating an integrated circuit to an electronic component. The systems and techniques include an integrated circuit configured to generate a system clock and an external clock having a programmable delay from the system clock. The integrated circuit may also be configured to provide the external clock to the electronic component to support communications therewith, communicate with the electronic component, and calibrate the external clock delay as a function of the communications.

    ADAPTIVE MEMORY CALIBRATION USING BINS

    公开(公告)号:CA2586537A1

    公开(公告)日:2006-05-18

    申请号:CA2586537

    申请日:2005-11-07

    Applicant: QUALCOMM INC

    Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

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