公开(公告)号：BRPI0907208A2

公开(公告)日：2015-07-14

申请号：BRPI0907208

申请日：2009-01-08

Applicant: QUALCOMM INC

Inventor： GU SIQUN ,  KANG SEUNG H ,  NORWAK MATTHEW M

IPC: H01L43/08

公开(公告)号：CA2711305C

公开(公告)日：2015-02-10

申请号：CA2711305

申请日：2009-01-08

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  KANG SEUNG H ,  NORWAK MATTHEW M

IPC: H01L43/08

Abstract: A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane.

公开(公告)号：CA2711305A1

公开(公告)日：2009-07-16

申请号：CA2711305

申请日：2009-01-08

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  KANG SEUNG H ,  NORWAK MATTHEW M

IPC: H01L43/08

Abstract: A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane.

公开(公告)号：WO2014110480A2

公开(公告)日：2014-07-17

申请号：PCT/US2014011223

申请日：2014-01-13

Applicant: QUALCOMM INC

Inventor： ZUO CHENGJIE ,  KIM JONGHAE ,  VELEZ MARIO FRANCISCO ,  LAN JE-HSIUNG ,  KIM DAEIK ,  YUN CHANGHAN ,  BERDY DAVID F ,  MIKULKA ROBERT P ,  NORWAK MATTHEW M ,  ZHANG XIANGDONG ,  SEE PUAY H

IPC: H03H7/46

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 直通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。