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    KERNEL MASKING OF DRAM DEFECTS
    1.
    发明申请
    KERNEL MASKING OF DRAM DEFECTS 审中-公开
    KERNEL屏蔽DRAM缺陷

    公开(公告)号：WO2015127274A1

    公开(公告)日：2015-08-27

    申请号：PCT/US2015/016913

    申请日：2015-02-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHUN, Dexter T. ,  LI, Yanru ,  DONG, Xiangyu ,  SUH, Jungwon ,  KIM, Jung Pill ,  SRIRAMAGIRI, Deepti Vijayalakshmi

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

    Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

    Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关联的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误数量超过错误计数阈值，则退出对应于物理地址的内核页面。

    METHODS AND APPARATUSES FOR IN-SYSTEM FIELD REPAIR AND RECOVERY FROM MEMORY FAILURES
    2.
    发明申请
    METHODS AND APPARATUSES FOR IN-SYSTEM FIELD REPAIR AND RECOVERY FROM MEMORY FAILURES 审中-公开
    用于系统现场修复和记忆故障恢复的方法和装置

    公开(公告)号：WO2015017156A1

    公开(公告)日：2015-02-05

    申请号：PCT/US2014/047435

    申请日：2014-07-21

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHUN, Dexter T. ,  SUH, Jungwon ,  MOLLOY, Stephen A. ,  KIM, Jung Pill

    IPC: G06F11/10 ,  G06F12/00 ,  G11C16/34

    CPC classification number: G06F3/0638 ,  G06F3/0617 ,  G06F3/0683 ,  G06F11/1048 ,  G06F12/0215 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/50016 ,  G11C2029/0409

    Abstract: In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.

    Abstract translation: 在特定实施例中，设备包括存储器地址重映射电路和重映射引擎。 存储器地址重映射电路包括比较电路，用于将接收到的存储器地址与一个或多个重映射地址进行比较。 存储器地址重映射电路还包括响应于比较电路的输出物理地址的选择电路。 物理地址对应于随机存取存储器（RAM）中的位置。 重映射引擎被配置为响应于检测到特定位置处的错误发生次数满足阈值而更新一个或多个重映射地址以包括特定地址。

    SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT
    3.
    发明申请
    SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT 审中-公开
    动态记忆功率管理系统与方法

    公开(公告)号：WO2014070264A1

    公开(公告)日：2014-05-08

    申请号：PCT/US2013/051231

    申请日：2013-07-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： LO, Haw-Jing ,  TAHA, Ali ,  CHUN, Dexter T.

    IPC: G06F1/32

    CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

    Abstract: Various embodiments of methods and systems for hardware (HW) based dynamic memory management in a portable computing device (PCD) are disclosed. One exemplary method includes generating a lookup table (LUT) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

    Abstract translation: 公开了在便携式计算设备（PCD）中基于硬件（HW）的动态存储器管理的方法和系统的各种实施例。 一种示例性方法包括生成查找表（LUT）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

    INTER-CHIP MEMORY INTERFACE STRUCTURE
    4.
    发明申请
    INTER-CHIP MEMORY INTERFACE STRUCTURE 审中-公开
    互联芯片内存接口结构

    公开(公告)号：WO2013181603A2

    公开(公告)日：2013-12-05

    申请号：PCT/US2013/043714

    申请日：2013-05-31

    Applicant: QUALCOMM INCORPORATED

    Inventor： SUH, Jungwon ,  CHUN, Dexter T.

    IPC: G11C5/04 ,  G06F13/16 ,  G06F13/42 ,  G11C5/06 ,  G11C7/10 ,  H01L27/00

    CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C7/222 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

    Abstract: In an embodiment, a stacked package-on-package system has a memory die (102; 104) and a logic die (106). The memory die comprises a first memory (306) and a second memory (308), each operated independently of the other, and each having an inter-chip interface (310; 312) electrically connected to the logic die. The logic die has two independent clock sources (318; 322), one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

    Abstract translation: 在一个实施例中，堆叠封装的封装系统具有存储管芯（102; 104）和逻辑管芯（106）。 存储器管芯包括第一存储器（306）和第二存储器（308），每个存储器（306）和第二存储器（308）独立于另一个独立地操作，并且每个具有电连接到逻辑管芯的芯片间接口（310; 312）。 逻辑管芯具有两个独立的时钟源（318; 322），一个用于向第一存储器提供第一时钟信号，另一个时钟源提供第二时钟信号给第二存储器。

    METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED
    6.
    发明申请
    METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED 审中-公开
    基于总线速度的双向总线上的选择性终止信号的方法和装置

    公开(公告)号：WO2014138477A1

    公开(公告)日：2014-09-12

    申请号：PCT/US2014/021401

    申请日：2014-03-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHUN, Dexter T. ,  SETHI, Sumeet S. ,  EATON, John D. ,  CUPPU, Vinodh R. ,  ARORA, Vikram ,  SRINIVAS, Vaishnav ,  MUNEER, Muhammad A. ,  BERK, Isaac D.

    IPC: G06F13/40

    CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

    Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。

    SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE
    7.
    发明申请
    SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE 审中-公开
    SERDES功率调节作为检测误差率的一种功能

    公开(公告)号：WO2012134652A2

    公开(公告)日：2012-10-04

    申请号：PCT/US2012/025526

    申请日：2012-02-16

    Applicant: QUALCOMM INCORPORATED ,  CHUN, Dexter T. ,  WOLF, Jack K. ,  SUH, Jungwon ,  SOWLATI, Tirdad

    Inventor： CHUN, Dexter T. ,  WOLF, Jack K. ,  SUH, Jungwon ,  SOWLATI, Tirdad

    IPC: H03M9/00 ,  H04W52/02

    CPC classification number: H04L12/12 ,  H04L1/0001 ,  H04L1/0036 ,  H04L25/02 ,  H04W52/0209 ,  Y02D70/00

    Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.

    Abstract translation: 系统包括从第一集成电路（IC）到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。 调整第一链路的电路中的功耗设置以控制功率消耗，使得第一链路的误码率保持在范围的下限范围远远大于零的范围内。 调整第二链路电路中的功耗设置以控制功耗，使得第二链路的误码率保持在范围内，其中范围的下限基本上大于零。 在一个示例中，第二IC中的电路检测第一链路中的错误并通过第二链路报告回来。 第一个IC使用报告的信息来确定第一个链路的误码率。

    METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED
    8.
    发明授权
    METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED 有权
    VEFAHREN和设备在双向总线基于CAN总线高速信号选择性终止

    公开(公告)号：EP2965217B1

    公开(公告)日：2017-04-19

    申请号：EP14716075.8

    申请日：2014-03-06

    Applicant: Qualcomm Incorporated

    Inventor： CHUN, Dexter T. ,  SETHI, Sumeet S. ,  EATON, John D. ,  CUPPU, Vinodh R. ,  ARORA, Vikram ,  SRINIVAS, Vaishnav ,  MUNEER, Muhammad A. ,  BERK, Isaac D.

    IPC: H03K19/0175 ,  H04L25/02

    CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

    Abstract translation: 控制信号终端的方法，包括：提供第一逻辑，用于选择性地终止于一个双向数据总线上的第一设备接收到的信号，用于选择性地终止于所述双向数据总线上的第二设备接收到的信号而提供第二逻辑，从所述第一设备发送第一信号 以第一速度的双向数据总线上的第二装置，停止所述第一信号的发送，停止所述第一信号的发送之后，使所述第二逻辑和从第一电平移位所述第二装置的参考电压施加到 第二电平，使所述第二逻辑在第二设备处，以更高的速度在双向数据总线上从所述第一设备发送第二信号到所述第二装置，并基于信号的速度控制第一逻辑之后在第一设备处接收到的 在双向数据总线。

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