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    DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION
    3.
    发明申请
    DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION 审中-公开
    DRAM SUB-ARRAY LEVEL AUTOMOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION

    公开(公告)号：WO2015005975A1

    公开(公告)日：2015-01-15

    申请号：PCT/US2014/038845

    申请日：2014-05-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： SRIRAMAGIRI, Deepti Vijayalakshmi ,  SUH, Jungwon ,  DONG, Xiangyu

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

    Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

    Abstract translation: 一种刷新动态随机存取存储器（DRAM）的方法包括在DRAM存储体的开放子阵列内检测DRAM存储体的一行的DRAM的开放页面。 该方法还包括当DRAM存储体的目标刷新行位于DRAM存储体的打开子阵列内时，延迟向DRAM存储体的目标刷新行发出刷新命令。

    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
    5.
    发明申请
    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：WO2019040183A1

    公开(公告)日：2019-02-28

    申请号：PCT/US2018/039978

    申请日：2018-06-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： SUH, Jungwon ,  ARTIERI, Alain ,  CHUN, Dexter Tamio ,  SRIRAMAGIRI, Deepti Vijayalakshmi

    IPC: G06F11/10

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    KERNEL MASKING OF DRAM DEFECTS
    7.
    发明申请
    KERNEL MASKING OF DRAM DEFECTS 审中-公开
    KERNEL屏蔽DRAM缺陷

    公开(公告)号：WO2015127274A1

    公开(公告)日：2015-08-27

    申请号：PCT/US2015/016913

    申请日：2015-02-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHUN, Dexter T. ,  LI, Yanru ,  DONG, Xiangyu ,  SUH, Jungwon ,  KIM, Jung Pill ,  SRIRAMAGIRI, Deepti Vijayalakshmi

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

    Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

    Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关联的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误数量超过错误计数阈值，则退出对应于物理地址的内核页面。

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