公开(公告)号：WO2016089539A1

公开(公告)日：2016-06-09

申请号：PCT/US2015/059198

申请日：2015-11-05

Applicant: QUALCOMM INCORPORATED

Inventor： ERTURK, Mete ,  SHENOY, Ravindra Vaman ,  LAI, Kwan-yu ,  KIM, Jitae ,  KIDWELL, JR., Donald William ,  LASITER, Jon Bradley ,  DOYLE, James Thomas ,  BCHIR, Omar James

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/00 ,  H05K1/16

CPC classification number: H01F27/2804 ,  H01F1/14708 ,  H01F5/00 ,  H01F17/0033 ,  H01F27/24 ,  H01F41/02 ,  H01F41/046 ,  H01F41/14 ,  H01F2017/002 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/165 ,  H05K1/182 ,  H05K2201/10166 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

Abstract translation: 电感器可以包括第一基板，磁片和导体。 第一衬底可以形成在第二衬底内。 磁片可以连接到第一衬底的第一侧。 导体可以形成在第二基板内，第二基板上，或两者上。 导体可以具有输入和输出。 导体可以被配置为围绕第一基板而不与第一基板接触，而不与磁片接触。

公开(公告)号：EP3254309A1

公开(公告)日：2017-12-13

申请号：EP16704361.1

申请日：2016-02-03

Applicant: Qualcomm Incorporated

Inventor： KIDWELL, Donald William, Jr. ,  SHENOY, Ravindra ,  ERTURK, Mete ,  ROUHANA, Layal

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  B23K26/0661 ,  H01F17/0033 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/585 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

公开(公告)号：WO2017039962A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/045998

申请日：2016-08-08

Applicant: QUALCOMM INCORPORATED

Inventor： ARABI, Karim ,  SHENOY, Ravindra Vaman ,  GOUSEV, Evgeni Petrovich ,  ERTURK, Mete

IPC: H01L23/64 ,  G06F1/32 ,  H02M1/00

CPC classification number: H01L28/10 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2224/16268 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.

Abstract translation: 具有线圈电感器的电压调节器集成或嵌入到片上系统（SOC）器件中。 线圈电感器制造在具有通孔的电感器晶片上，并且电感器晶片与SOC晶片连接以与SOC器件集成。

公开(公告)号：WO2016126881A1

公开(公告)日：2016-08-11

申请号：PCT/US2016/016458

申请日：2016-02-03

Applicant: QUALCOMM INCORPORATED

Inventor： KIDWELL, Donald William, Jr. ,  SHENOY, Ravindra ,  ERTURK, Mete ,  ROUHANA, Layal

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  B23K26/0661 ,  H01F17/0033 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/585 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Abstract translation: 集成器件封装包括管芯和封装衬底。 封装衬底包括至少一个电介质层（例如芯层，预镀层），电介质层中的磁芯，被配置为作为第一保护环工作的第一多个互连件和被构造成操作的第二多个互连件 作为第一电感器。 所述第二多个互连件定位在所述封装衬底中以至少部分地围绕所述磁芯。 来自第二多个互连的至少一个互连也是第一多个互连的一部分。 在一些实施方案中，第一保护环是不连续的保护环。 在一些实施方式中，第一电感器是螺线管电感器。 在一些实施方案中，磁芯包括载体，第一磁性层和第二磁性层。

公开(公告)号：EP3345218A1

公开(公告)日：2018-07-11

申请号：EP16751137.7

申请日：2016-08-08

Applicant: Qualcomm Incorporated

Inventor： ARABI, Karim ,  SHENOY, Ravindra Vaman ,  GOUSEV, Evgeni Petrovich ,  ERTURK, Mete

IPC: H01L23/64 ,  G06F1/32 ,  H02M1/00

CPC classification number: H01L28/10 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2224/16268 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.