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公开(公告)号：WO2019133474A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/067063
申请日：2018-12-21
Applicant: QUALCOMM INCORPORATED
Inventor： KARMAKER, Rahul , FAN, Bin
IPC: H03F3/45
CPC classification number: H03F1/0205 , H03F3/193 , H03F3/4521 , H03F3/45237 , H03F3/4565 , H03F2200/36 , H03F2200/411 , H03F2200/451 , H03F2200/453 , H03F2200/456 , H03F2200/555 , H03F2203/45022 , H03F2203/45026 , H03F2203/45082 , H03F2203/45172 , H03F2203/45188 , H03F2203/45288 , H03F2203/45418 , H03F2203/45424 , H03F2203/45494 , H03F2203/45508
Abstract: Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.
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公开(公告)号：WO2016069165A1
公开(公告)日：2016-05-06
申请号：PCT/US2015/052717
申请日：2015-09-28
Applicant: QUALCOMM INCORPORATED
Inventor： LAKDAWALA, Hasnain Mohammedi , FAN, Bin , CHOKSI, Ojas Mahendra
CPC classification number: H03D7/1441 , H03D3/009 , H03D7/1458 , H03D7/1466 , H03D7/165 , H04B1/40 , H04L27/206 , H04L27/2089
Abstract: Performing quadrature combining and adjusting including: a plurality of mixing circuits configured to generate a plurality of frequency converted signals; at least one mixing circuit of the plurality of mixing circuits is configured with a plurality of paths, each path representing one linearity mode; and a plurality of combining circuits configured to combine the plurality of frequency converted signals to generate a differential baseband output signal.
Abstract translation: 执行正交组合和调整包括：多个混合电路，被配置为产生多个频率转换信号; 多个混合电路中的至少一个混频电路配置有多个路径，每个路径表示一个线性模式; 以及多个组合电路，被配置为组合多个频率转换信号以产生差分基带输出信号。
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公开(公告)号：WO2016069172A1
公开(公告)日：2016-05-06
申请号：PCT/US2015/052904
申请日：2015-09-29
Applicant: QUALCOMM INCORPORATED
Inventor： CHOKSI, Ojas Mahendra , FAN, Bin , HANAFI, Bassel
CPC classification number: H03F1/565 , H03F1/3211 , H03F1/347 , H03F3/193 , H03F3/195 , H03F3/45071 , H03F3/45188 , H03F3/45475 , H03F2200/294 , H03F2200/301 , H03F2200/451 , H03F2200/54 , H03F2203/21112 , H03F2203/45306 , H03F2203/45318 , H03F2203/45386 , H03F2203/45562 , H03F2203/45616 , H03F2203/45621 , H04B1/525
Abstract: An apparatus (400) includes: first and second transistors (410, 412), each of the first and second transistors (410, 412) includes a gate terminal, a source terminal, and a drain terminal; and a transformer (420) including a primary winding (422) and first and second secondary windings (424, 426), the primary winding (422) is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings (424, 426) are coupled to gate terminals of the first and second transistors (410, 412) and cross-coupled to source terminals of the first and second transistors (410, 412).
Abstract translation: 装置（400）包括：第一和第二晶体管（410,412），第一和第二晶体管（410,412）中的每一个包括栅极端子，源极端子和漏极端子; 以及包括初级绕组（422）和第一和第二次级绕组（424,426）的变压器（420），所述初级绕组（422）耦合到被配置为接收输入信号的第一输入节点和配置的第二输入节点 为了接收电位，第一和第二次级绕组（424,426）耦合到第一和第二晶体管（410,412）的栅极端子并交叉耦合到第一和第二晶体管（410,412）的源极端子， 。
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公开(公告)号：EP3213409A1
公开(公告)日：2017-09-06
申请号：EP15778516.3
申请日：2015-09-28
Applicant: Qualcomm Incorporated
Inventor： LAKDAWALA, Hasnain Mohammedi , FAN, Bin , CHOKSI, Ojas Mahendra
CPC classification number: H03D7/1441 , H03D3/009 , H03D7/1458 , H03D7/1466 , H03D7/165 , H04B1/40 , H04L27/206 , H04L27/2089
Abstract: Performing quadrature combining and adjusting including: a plurality of mixing circuits configured to generate a plurality of frequency converted signals; at least one mixing circuit of the plurality of mixing circuits is configured with a plurality of paths, each path representing one linearity mode; and a plurality of combining circuits configured to combine the plurality of frequency converted signals to generate a differential baseband output signal.
Abstract translation: 执行正交组合和调整，包括：多个混频电路，被配置为生成多个频率转换信号; 所述多个混合电路中的至少一个混合电路配置有多个路径，每个路径表示一个线性模式; 以及多个组合电路，被配置为组合多个频率转换的信号以生成差分基带输出信号。
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公开(公告)号：WO2016076981A1
公开(公告)日：2016-05-19
申请号：PCT/US2015/054273
申请日：2015-10-06
Applicant: QUALCOMM INCORPORATED
Inventor： CHOKSI, Ojas Mahendra , FAN, Bin , HANAFI, Bassel , LAKDAWALA, Hasnain Mohammedi , AKULA, Prashanth , SABOURI, Faramarz
IPC: H04B1/16
CPC classification number: H04B1/16 , H04B1/1018 , H04B1/1027 , H04B1/1638 , H04B2001/0416
Abstract: An apparatus including: at least one differential amplifier configured to amplify a radio frequency signal; a mixer configured to mix the radio frequency signal from the at least one differential amplifier with a local oscillator signal; and a low-pass filter coupled to the mixer, the low-pass filter includes a capacitor and at least one variable resistor configured to tune the low-pass filter.
Abstract translation: 一种装置，包括：至少一个差分放大器，被配置为放大射频信号; 配置为将来自所述至少一个差分放大器的射频信号与本地振荡器信号混合的混频器; 以及耦合到混频器的低通滤波器，低通滤波器包括电容器和配置成调谐低通滤波器的至少一个可变电阻器。
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Patent Agency Ranking6.发明申请
公开(公告)号：WO2014018178A1
公开(公告)日：2014-01-30
申请号：PCT/US2013/045375
申请日：2013-06-12
Applicant: QUALCOMM INCORPORATED
Inventor： FAN, Bin , TANG, Yiwu , WANG, Kevin Hsi Huai
CPC classification number: H03L3/00 , H04W52/029 , Y02D70/00 , Y02D70/122 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164
Abstract: A system (10) for managing a reference clock signal includes an XO (22), a signal buffer (24) coupled to the XO (22) and configured to drive a reference clock signal generated by the XO (22), and a first IC (12) coupled to the signal buffer (24). The first IC (12) includes an XO input buffer (32) configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit (34) configured to be in an enabled, operational state when the XO input buffer (32) is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism (36) configured to switch the XO input buffer (32) and the impedance equivalence circuit (34) between the enabled state and the disabled state.
Abstract translation: 用于管理参考时钟信号的系统（10）包括XO（22），耦合到XO（22）并被配置为驱动由XO（22）产生的参考时钟信号的信号缓冲器（24），以及第一 IC（12）耦合到信号缓冲器（24）。 第一IC（12）包括被配置为接收参考时钟信号的XO输入缓冲器（32），以在启用状态，操作状态和禁用状态之间切换，并且在处于使能状态时具有第一操作阻抗; 阻抗等效电路（34）被配置为当XO输入缓冲器（32）处于其禁用状态并且反之亦然时处于使能的操作状态，并且具有第二操作阻抗，同时处于使能状态，等效于第一 工作阻抗; 以及配置为在所述使能状态和所述禁用状态之间切换所述XO输入缓冲器（32）和所述阻抗等效电路（34）的控制机构（36）。
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公开(公告)号：EP3213410A1
公开(公告)日：2017-09-06
申请号：EP15778536.1
申请日：2015-09-29
Applicant: Qualcomm Incorporated
Inventor： CHOKSI, Ojas Mahendra , FAN, Bin , HANAFI, Bassel
CPC classification number: H03F1/565 , H03F1/3211 , H03F1/347 , H03F3/193 , H03F3/195 , H03F3/45071 , H03F3/45188 , H03F3/45475 , H03F2200/294 , H03F2200/301 , H03F2200/451 , H03F2200/54 , H03F2203/21112 , H03F2203/45306 , H03F2203/45318 , H03F2203/45386 , H03F2203/45562 , H03F2203/45616 , H03F2203/45621 , H04B1/525
Abstract: An apparatus includes: first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal; and a transformer including a primary winding and first and second secondary windings, the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors.
Abstract translation: 一种装置包括：第一和第二晶体管，第一和第二晶体管中的每一个包括栅极端子，源极端子和漏极端子; 以及包括初级绕组以及第一和第二次级绕组的变压器，所述初级绕组耦合到被配置为接收输入信号的第一输入节点和被配置为接收电位的第二输入节点，所述第一和第二次级绕组耦合到 第一和第二晶体管的栅极端子并交叉耦合到第一和第二晶体管的源极端子。
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公开(公告)号：EP3732782A1
公开(公告)日：2020-11-04
申请号：EP18837050.6
申请日：2018-12-21
Applicant: QUALCOMM INCORPORATED
Inventor： KARMAKER, Rahul , FAN, Bin
IPC: H03F3/45
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公开(公告)号：EP3219018A1
公开(公告)日：2017-09-20
申请号：EP15787073.4
申请日：2015-10-06
Applicant: Qualcomm Incorporated
Inventor： CHOKSI, Ojas Mahendra , FAN, Bin , HANAFI, Bassel , LAKDAWALA, Hasnain Mohammedi , AKULA, Prashanth , SABOURI, Faramarz
IPC: H04B1/16
CPC classification number: H04B1/16 , H04B1/1018 , H04B1/1027 , H04B1/1638 , H04B2001/0416
Abstract: An apparatus including: at least one differential amplifier configured to amplify a radio frequency signal; a mixer configured to mix the radio frequency signal from the at least one differential amplifier with a local oscillator signal; and a low-pass filter coupled to the mixer, the low-pass filter includes a capacitor and at least one variable resistor configured to tune the low-pass filter.
Abstract translation: 一种设备，包括：至少一个差分放大器，被配置为放大射频信号; 混频器，被配置为将来自所述至少一个差分放大器的射频信号与本地振荡器信号混频; 以及耦合到所述混频器的低通滤波器，所述低通滤波器包括电容器和被配置为调谐所述低通滤波器的至少一个可变电阻器。
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公开(公告)号：EP3213409B1
公开(公告)日：2019-01-02
申请号：EP15778516.3
申请日：2015-09-28
Applicant: Qualcomm Incorporated
Inventor： LAKDAWALA, Hasnain Mohammedi , FAN, Bin , CHOKSI, Ojas Mahendra
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