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    INTEGRATED DEVICE COMPRISING PILLAR INTERCONNECTS WITH VARIABLE SHAPES
    2.
    发明申请
    INTEGRATED DEVICE COMPRISING PILLAR INTERCONNECTS WITH VARIABLE SHAPES 审中-公开

    公开(公告)号：WO2023043556A1

    公开(公告)日：2023-03-23

    申请号：PCT/US2022/040349

    申请日：2022-08-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHEN, Yujen ,  HSU, Hung-Yuan ,  HE, Dongming

    IPC: H01L23/485 ,  H01L21/60

    Abstract: An integrated device (100, 300, 800) comprises: a die portion (102) comprising a plurality of pads (107) and a plurality of under bump metallization interconnects (109) coupled to the plurality of pads (107); and a plurality of pillar interconnects (104, 304) coupled to the plurality of under bump metallization interconnects (109), wherein the plurality of pillar interconnects (104, 304) includes a first pillar interconnect (104a, 304a) comprising: a first pillar interconnect portion (204, 404) comprising a first width and a second pillar interconnect portion (206, 406) comprising a second width that is different than the first width. The first width may be greater than the second width, wherein the first pillar interconnect (304a) may be configured to provide an electrical path for input / output (I/O) signals to and/or from the integrated device (300). The first width may be less than the second width (e.g., the first pillar interconnect (104a) comprising a cross-sectional side profile having a T shape), in which case the first pillar interconnect (104a) may be configured to provide an electrical path for power to the integrated device (100). The first width may also be greater than the second width and the plurality of pillar interconnects include a second pillar interconnect (104b) comprising: a third pillar interconnect portion comprising a third width and a fourth pillar interconnect portion comprising a fourth width that is greater than the third width, wherein the first pillar interconnect (304a) may be configured to provide an electrical path for power to the integrated device (800) and wherein the second pillar interconnect (104b) may be configured to provide an electrical path for input / output (I/O) signals to and/or from the integrated device (800). The integrated device (100, 300, 800) may be coupled to a substrate (502) through the plurality of pillar interconnects (104, 304) and a plurality of solder interconnects (106), forming a package (500). In a method for fabricating the integrated device (100, 300, 800), forming the plurality of pillar interconnects (104, 304) comprises: forming and patterning a first photo resist layer (900) over the die portion (102); forming the first pillar interconnect portion (902); removing the first photo resist layer (900); forming a second photo resist layer (906) over the die portion (102); forming and patterning a third photo resist layer (910) over the second photo resist layer (906); and forming a second pillar interconnect portion (912) over the first pillar interconnect portion (902) through an opening (911) in the third photo resist layer (910). The second photo resist layer (906) may include a positive photo resist layer and the third photo resist layer (910) may include a negative photo resist layer. The second photo resist layer (906) may also include a negative photo resist layer and the third photo resist layer (910) may include a positive photo resist layer. The different and/or varying widths of the pillar interconnect portions may allow more surface area for the solder interconnects (106) to couple to, thus providing a more robust and reliable joint between the integrated device (100, 300, 800) and the substrate (502). The increased surface area may also allow more solder to be located between the first pillar interconnect (104, 304) and the substrate (502), without causing a short between neighboring interconnects. The more robust and reliable joint helps provide a more reliable electrical path for currents and/or signals traveling between the integrated device (100, 300, 800) and the substrate (502), which can lead to improved performances for the integrated device (100, 300, 800) and the package (500).

    INTEGRATED DEVICE COMPRISING PILLAR INTERCONNECT WITH CAVITY
    6.
    发明申请
    INTEGRATED DEVICE COMPRISING PILLAR INTERCONNECT WITH CAVITY 审中-公开

    公开(公告)号：WO2023027811A1

    公开(公告)日：2023-03-02

    申请号：PCT/US2022/035751

    申请日：2022-06-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHEN, Yujen ,  HSU, Hung-Yuan ,  HE, Dongming

    IPC: H01L23/485 ,  H01L21/60

    Abstract: An integrated device (e.g., a flip chip) (100) comprises: a die portion (102) comprising a plurality of pads (107a, 107b) and a plurality of under bump metallization interconnects (109a, 109b) coupled to the plurality of pads (107a, 107b); and a plurality of pillar interconnects (104a, 104b) coupled to the plurality of under bump metallization interconnects (109a, 109b), wherein the plurality of pillar interconnects (104a, 104b) comprises a first pillar interconnect (104a) comprising a first cavity (209) and a second pillar interconnect (104b) comprising a second cavity (209). The cavity (209) may extend partially through a height of the pillar interconnect (104a, 104b). A planar cross section that extends through the cavity (209) of the pillar interconnect (104a, 104b) may comprise an O shape. A plurality of solder interconnects (106a, 106b) may be coupled to the plurality of pillar interconnects (104a, 104b) and may comprise solder interconnects (106a, 106b) located in the cavities (209) of the pillar interconnects (104a, 104b). The pillar interconnect (104a, 104b) may comprise: a first pillar interconnect portion (204) comprising a first width; and a second pillar interconnect portion (206) comprising a second width that is different (e.g., smaller) than the first width, wherein the cavity (209) of the pillar interconnect (104a, 104b) may be located in the second pillar interconnect portion (206). The pillar interconnect (104a, 104b) may comprise a shape of a top hat. A method (700) for fabricating the integrated device (100) may comprise providing the die portion (102) and forming the plurality of pillar interconnects (104). Forming the plurality of pillar interconnects (104) may comprise: forming and patterning a first photoresist layer (600) over the die portion (102); forming a first pillar interconnect portion (602) (e.g., ring-shaped); removing the first photoresist layer (600); forming and patterning a second photoresist layer (610) over the die portion (102) (e.g., with a circular pattern with a diameter between the inner and outer diameter of the ring-shaped first interconnect portion (602)); and forming a second pillar interconnect portion over the first pillar interconnect portion (602) such that the first cavity (209) is formed in the second pillar interconnect portion. Forming the plurality of pillar interconnects (104) may further comprise forming the solder interconnects (106) over the cavities (209) of the pillar interconnects (104). The second photoresist layer (610) may be removed after the formation of the first solder interconnects (106). Portions of the under bump metallization layer (109) may then be removed and the plurality of solder interconnects (106) may be reflowed. A package (400) comprises a substrate (402) and the integrated device (100) coupled to the substrate (402) through the plurality of pillar interconnects (104a, 104b) and the plurality of solder interconnects (106a, 106b). The solder interconnect (106a, 106b) may comprise an intermetallic compound (IMC) (406a, 406b), which may be formed when metal from a substrate interconnect (422a, 422b) and/or the pillar interconnect (104a, 104b) diffuses in the solder interconnect (106a, 106b) upon solder reflow process used to couple the integrated device (100) to the substrate (402). The cavities (209) allow more surface area for the solder interconnects (106a, 106b) to couple to, thus providing a more robust and reliable joint between the integrated device (100) and the substrate (402). The cavities (209) also allow more solder interconnect (106a, 106b) to be located between the pillar interconnects (104a, 104b) and the substrate (402), without causing a short between neighbouring interconnects (104a, 104b) of the substrate (402).

    INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A THERMAL CONDUCTIVE PACKAGE SUBSTRATE WITH DIE REGION SPLIT, AND RELATED FABRICATION METHODS
    7.
    发明申请
    INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A THERMAL CONDUCTIVE PACKAGE SUBSTRATE WITH DIE REGION SPLIT, AND RELATED FABRICATION METHODS 审中-公开

    公开(公告)号：WO2021158282A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2020/063935

    申请日：2020-12-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  PATIL, Aniket ,  YAN, Bohan ,  HE, Dongming

    IPC: H01L23/367

    Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layer in the package substrate may also include dielectric materials having different thermal conductivities to further facilitate thermal dissipation and/or desired electrical or mechanical characteristics.

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