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    FAST FOURIER TRANSFORM USING PHASOR TABLE
    1.
    发明申请
    FAST FOURIER TRANSFORM USING PHASOR TABLE 审中-公开

    公开(公告)号：WO2023049594A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/075410

    申请日：2022-08-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： SRINIVASAN, Santosh Srivatsan ,  HOFFMAN, Marc ,  SUDARSANAN, Srijesh ,  MATHEW, Deepak ,  DONG, Hongfeng ,  SWEENEY, Gerald

    IPC: G06F17/14 ,  G06F9/00

    Abstract: A device includes a memory configured to store a fast Fourier transform (FFT) instruction and parameters of the FFT instruction, a read-only memory including a phasor table, and a processor. The processor is configured to execute the FFT instruction to determine, based on the parameters of the FFT instruction, a start value and a step size. The processor is configured to execute the FFT instruction to access the phasor table according to the start value and the step size to obtain a set of twiddle values. The processor is also configured to execute the FFT instruction to compute, for each pair of input values in a set of input data, an output value based on the pair of input values and a twiddle value, of the set of twiddle values, that corresponds to that pair of input values.

    PERMUTATION INSTRUCTION
    4.
    发明申请
    PERMUTATION INSTRUCTION 审中-公开

    公开(公告)号：WO2023049593A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/075406

    申请日：2022-08-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： SUDARSANAN, Srijesh ,  MATHEW, Deepak ,  HOFFMAN, Marc ,  SWEENEY, Gerald ,  BALASUBRAMANIAN, Sundar Rajan ,  DONG, Hongfeng ,  SUN, Yurong ,  SADEGHZADEH, Seyedmehdi

    IPC: G06F9/30

    Abstract: A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

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