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    INTEGRATED INTERPOSER WITH EMBEDDED ACTIVE DEVICES
    2.
    发明申请
    INTEGRATED INTERPOSER WITH EMBEDDED ACTIVE DEVICES 审中-公开
    具有嵌入式有源器件的集成式插补器

    公开(公告)号：WO2015130680A1

    公开(公告)日：2015-09-03

    申请号：PCT/US2015/017320

    申请日：2015-02-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAMACHANDRAN, Vidhya ,  RAY, Urmi ,  SHENOY, Ravindra Vaman ,  LAI, Kwan-Yu ,  LASITER, Jon Bradley

    IPC: H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/768

    CPC classification number: H05K1/185 ,  H01L21/28008 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/065 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/12 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.

    Abstract translation: 第一部件和第二部件之间的集成插入件包括基板。 衬底可以具有热和/或机械性质，其值位于第一部件和第二部件的热和/或机械性能之间。 有源器件设置在衬底的第一表面上。 接触层耦合到有源器件并且被配置为将至少第一部件和第三部件耦合到集成插入器。 至少一个通孔连接到接触层并且延伸穿过衬底到衬底的第二表面。 互连层设置在衬底的第二表面上并且耦合到至少一个通孔。 互连层被配置为将第二组件耦合到集成插入器。

    TOROID INDUCTOR IN REDISTRIBUTION LAYERS (RDL) OF AN INTEGRATED DEVICE
    3.
    发明申请
    TOROID INDUCTOR IN REDISTRIBUTION LAYERS (RDL) OF AN INTEGRATED DEVICE 审中-公开
    一体化设备的重分布层（RDL）中的电导电感器

    公开(公告)号：WO2015112510A1

    公开(公告)日：2015-07-30

    申请号：PCT/US2015/012090

    申请日：2015-01-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： GU, Shiqun ,  LANE, Ryan David ,  RAY, Urmi

    IPC: H01L23/538 ,  H01L49/02

    CPC classification number: H01L23/5227 ,  H01L21/76838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L28/10 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

    Abstract translation: 一些特征涉及集成器件，其包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层，耦合到金属层中的一个的第一金属再分布层，以及耦合到衬底的第二金属再分配层 第一金属再分配层。 第一和第二金属再分布层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，集成器件还包括第三金属再分配层。 第三金属再分布层耦合到第一和第二金属再分配层。 第三金属再分配层是通孔。 在一些实施方案中，第一，第二和第三金属再分配层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，第一，第二和第三再分配层形成用于环形电感器的一组绕组。

    STRESS BALANCE LAYER ON SEMICONDUCTOR WAFER BACKSIDE
    4.
    发明申请
    STRESS BALANCE LAYER ON SEMICONDUCTOR WAFER BACKSIDE 审中-公开

    公开(公告)号：WO2010144848A3

    公开(公告)日：2010-12-16

    申请号：PCT/US2010/038383

    申请日：2010-06-11

    Applicant: QUALCOMM Incorporated ,  GU, Shiqun ,  CHANDRASEKARAN, Arvind ,  RAY, Urmi ,  LI, Yiming

    Inventor： GU, Shiqun ,  CHANDRASEKARAN, Arvind ,  RAY, Urmi ,  LI, Yiming

    IPC: H01L23/00

    Abstract: A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.

    LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER
    5.
    发明公开
    LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER 审中-公开
    与氧化层的低成本ZWISCHENSTÜCK

    公开(公告)号：EP2984679A1

    公开(公告)日：2016-02-17

    申请号：EP14722935.5

    申请日：2014-04-08

    Applicant: Qualcomm Incorporated

    Inventor： GU, Shiqun ,  RAY, Urmi ,  CHEN, Roawen ,  HENDERSON, Brian Matthew ,  RADOJCIC, Ratibor ,  NOWAK, Matthew ,  YU, Nicholas

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.

    THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM
    6.
    发明申请
    THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
    通过硅胶制成的薄膜

    公开(公告)号：WO2011116326A1

    公开(公告)日：2011-09-22

    申请号：PCT/US2011/029058

    申请日：2011-03-18

    Applicant: QUALCOMM Incorporated ,  GU, Shiqun ,  LI, Yiming ,  RAY, Urmi

    Inventor： GU, Shiqun ,  LI, Yiming ,  RAY, Urmi

    IPC: H01L21/768

    CPC classification number: H01L21/76898

    Abstract: For a semiconductor wafer substrate (102) having an inter layer dielectric (110), a through - silicon via may be formed in the substrate by first depositing an etch stop film (202) on top of the inter layer dielectric, followed by etching an opening (204) through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner (206) is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material (208) may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.

    Abstract translation: 对于具有层间电介质（110）的半导体晶片基板（102），可以通过首先在层间电介质的顶部上沉积蚀刻停止膜（202），然后蚀刻 通过蚀刻停止膜，层间电介质，并进入衬底的开口（204）。 然后将电介质衬垫（206）沉积在蚀刻停止膜上并进入开口中。 对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。 然后可以将导电材料（208）沉积到开口中和蚀刻停止膜上。 然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

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