公开(公告)号：WO2014004162A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/046283

申请日：2013-06-18

Applicant: RAYTHEON COMPANY

Inventor： DIEP, Buu ,  BLACK, Stephen H.

IPC: H01L21/56

CPC classification number: G01J5/0235 ,  G01J5/024 ,  G01J5/045 ,  G01J5/20 ,  G01J2005/202 ,  H01L31/0203 ,  H01L31/09 ,  H01L2924/0002 ,  H01L2924/0001

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract translation: 一种形成半导体器件的盖帽晶片（WCW）结构的方法包括将多个空腔加工成第一基板的正面; 在第一基板的前侧将第一基板接合到第二基板; 去除第一基板的背面以露出多个空腔，从而限定包括第二基板的WCW结构和由第一基板的材料构成的多个垂直支撑件。

公开(公告)号：WO2014070534A2

公开(公告)日：2014-05-08

申请号：PCT/US2013/066266

申请日：2013-10-23

Applicant: RAYTHEON COMPANY

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract translation: 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。

公开(公告)号：WO2013192132A1

公开(公告)日：2013-12-27

申请号：PCT/US2013/046231

申请日：2013-06-18

Applicant: RAYTHEON COMPANY

Inventor： BLACK, Stephen H. ,  GRITZ, Michael A. ,  KENNEDY, Adam M.

IPC: H01L27/146

CPC classification number: G01S13/89 ,  G01S2007/028 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01Q1/2283 ,  H01Q21/0006

Abstract: A receiver chip for use in an imaging system includes a plurality of receiver dies, each of the receiver dies comprising one or more receiver circuits; a die interconnection layer located on top of the plurality of receiver dies; a quarter wave dielectric layer located on top of the die interconnection layer; and a plurality of antennae located on the quarter wave dielectric layer, each of the plurality of antennae corresponding to a respective receiver circuit, wherein the plurality of antennae are connected to the one or more receiver circuits through the quarter wave dielectric layer and the die interconnection layer by respective vias, such that a distance between a topmost layer of the die interconnection layer and the plurality of antennae is determined by a thickness of the quarter wave dielectric layer.

Abstract translation: 用于成像系统的接收器芯片包括多个接收器管芯，每个接收器管芯包括一个或多个接收器电路; 位于所述多个接收器管芯的顶部上的管芯互连层; 位于芯片互连层顶部的四分之一波长介电层; 以及位于所述四分之一波长介电层上的多个天线，所述多个天线中的每一个对应于相应的接收器电路，其中所述多个天线通过所述四分之一波长介电层连接到所述一个或多个接收器电路，并且所述管芯互连 使得芯片互连层的最上层与多个天线之间的距离由四分之一波长介电层的厚度确定。

公开(公告)号：EP3111179A1

公开(公告)日：2017-01-04

申请号：EP15710030.6

申请日：2015-02-20

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  KENNEDY, Adam M. ,  BLACK, Stephen H. ,  KOCIAN, Thomas Allan ,  DIEP, Buu

IPC: G01J5/04 ,  G02B19/00 ,  H01L23/26

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract translation: 一种吸气剂结构和方法，其中在结构的表面上形成多个成核位置的条件下，将种子材料层沉积在结构的表面的预定区域上。 成核位置具有小于一分子厚的预定区域的表面积的平均高度。 随后，吸附剂材料沉积在表面上以形成从成核位置向外突出的多个吸气材料构件。

公开(公告)号：EP2915190A2

公开(公告)日：2015-09-09

申请号：EP13850327.1

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：EP2865002A1

公开(公告)日：2015-04-29

申请号：EP13809283.8

申请日：2013-06-18

Applicant: Raytheon Company

Inventor： DIEP, Buu ,  BLACK, Stephen H.

IPC: H01L21/56

CPC classification number: G01J5/0235 ,  G01J5/024 ,  G01J5/045 ,  G01J5/20 ,  G01J2005/202 ,  H01L31/0203 ,  H01L31/09 ,  H01L2924/0002 ,  H01L2924/0001

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract translation: 一种形成用于半导体器件的窗口帽晶片（WCW）结构的方法包括：将多个空腔加工到第一衬底的正面; 在第一基板的正面将第一基板粘合到第二基板; 去除所述第一基板的背面以露出所述多个空腔，由此限定包括所述第二基板和由所述第一基板的材料构成的多个垂直支撑件的WCW结构。

公开(公告)号：EP2862204A1

公开(公告)日：2015-04-22

申请号：EP13806576.8

申请日：2013-06-18

Applicant: Raytheon Company

Inventor： BLACK, Stephen H. ,  GRITZ, Michael A. ,  KENNEDY, Adam M.

IPC: H01L27/146

CPC classification number: G01S13/89 ,  G01S2007/028 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01Q1/2283 ,  H01Q21/0006

Abstract: A receiver chip for use in an imaging system includes a plurality of receiver dies, each of the receiver dies comprising one or more receiver circuits; a die interconnection layer located on top of the plurality of receiver dies; a quarter wave dielectric layer located on top of the die interconnection layer; and a plurality of antennae located on the quarter wave dielectric layer, each of the plurality of antennae corresponding to a respective receiver circuit, wherein the plurality of antennae are connected to the one or more receiver circuits through the quarter wave dielectric layer and the die interconnection layer by respective vias, such that a distance between a topmost layer of the die interconnection layer and the plurality of antennae is determined by a thickness of the quarter wave dielectric layer.

公开(公告)号：EP2865002B1

公开(公告)日：2019-03-20

申请号：EP13809283.8

申请日：2013-06-18

Applicant: Raytheon Company

Inventor： DIEP, Buu ,  BLACK, Stephen H.

IPC: H01L21/56 ,  G01J5/02

公开(公告)号：EP2705657B1

公开(公告)日：2018-08-15

申请号：EP12727697.0

申请日：2012-05-04

Applicant: Raytheon Company

Inventor： KENNEDY, Adam ,  BLACK, Stephen H. ,  BAUR, Stefan T.

IPC: H04N5/33 ,  H04N5/335 ,  H04N5/225 ,  H01L27/146

CPC classification number: H04N5/2257 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48465 ,  H04N5/33 ,  H04N5/335 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to some embodiments, a camera includes a multi-chip system in a package (MCSiP). The MCSiP comprising a set of electronics, an encapsulate, and a plurality of interconnects. The set of electronics includes a plurality of bare integrated circuit dies and other passive or active electronic components. Each die is operable to provide a functional component of a computing system operable to receive a signal describing electromagnetic radiation detected by an imaging sensor and facilitate generating an image according to the signal. The encapsulate comprises an adhesive molding compound deposited outwardly from the set of electronics in order to hold the set of electronics in position. The interconnects communicatively couple each die to other dies, the other electronic components, or components external to the MCSiP.

公开(公告)号：EP3340294A1

公开(公告)日：2018-06-27

申请号：EP18155856.0

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device ,the method comprising forming a device wafer, forming a cap wafer,forming a cap wafer, forming,on either, one or more material layers used in the formation of either the cap wafer or the device wafer, and left remaining in a region of a substrate of either the cap wafer or the device wafer, and bonding the cap wafer to the device wafer.