公开(公告)号：WO2014070534A2

公开(公告)日：2014-05-08

申请号：PCT/US2013/066266

申请日：2013-10-23

Applicant: RAYTHEON COMPANY

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract translation: 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。

公开(公告)号：WO2016209339A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/028338

申请日：2016-04-20

Applicant: RAYTHEON COMPANY

Inventor： DIEP, Buu Q. ,  KENNEDY, Adam M. ,  KOCIAN, Thomas Allan ,  LAMB, Mark

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81B7/0041 ,  B81B2201/0207 ,  B81B2201/04 ,  B81C1/00269 ,  B81C1/00317 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0145 ,  B81C2203/019

Abstract: A microelectromechanical systems (MEMS) package includes a substrate extending between a first pair of outer edges to define a length and a second pair of outer edges to define a width. A seal ring assembly is disposed on the substrate and includes at least one seal ring creating a first boundary point adjacent to at least one MEMS device and a second boundary point adjacent at least one of the outer edges. The package further includes a window lid on the seal ring assembly to define a seal gap containing the at least one MEMS device. The seal ring assembly anchors the window lid to the substrate at the second boundary point such that deflection of the window lid into the seal gap is reduced.

Abstract translation: 微机电系统（MEMS）封装包括在第一对外边缘之间延伸以限定长度的基板和限定宽度的第二对外边缘。 密封环组件设置在基板上，并且包括至少一个密封环，其形成与至少一个MEMS装置相邻的第一边界点和邻近至少一个外边缘的第二边界点。 封装还包括在密封环组件上的窗口盖，以限定包含至少一个MEMS器件的密封间隙。 密封圈组件在第二边界点将窗口盖固定到基底，使得窗口盖进入密封间隙的偏转减小。

公开(公告)号：EP3340294A1

公开(公告)日：2018-06-27

申请号：EP18155856.0

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device ,the method comprising forming a device wafer, forming a cap wafer,forming a cap wafer, forming,on either, one or more material layers used in the formation of either the cap wafer or the device wafer, and left remaining in a region of a substrate of either the cap wafer or the device wafer, and bonding the cap wafer to the device wafer.

公开(公告)号：EP3111179A1

公开(公告)日：2017-01-04

申请号：EP15710030.6

申请日：2015-02-20

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  KENNEDY, Adam M. ,  BLACK, Stephen H. ,  KOCIAN, Thomas Allan ,  DIEP, Buu

IPC: G01J5/04 ,  G02B19/00 ,  H01L23/26

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract translation: 一种吸气剂结构和方法，其中在结构的表面上形成多个成核位置的条件下，将种子材料层沉积在结构的表面的预定区域上。 成核位置具有小于一分子厚的预定区域的表面积的平均高度。 随后，吸附剂材料沉积在表面上以形成从成核位置向外突出的多个吸气材料构件。

公开(公告)号：EP2915190A2

公开(公告)日：2015-09-09

申请号：EP13850327.1

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：EP3111179B1

公开(公告)日：2020-07-22

申请号：EP15710030.6

申请日：2015-02-20

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  KENNEDY, Adam M. ,  BLACK, Stephen H. ,  KOCIAN, Thomas Allan ,  DIEP, Buu

IPC: G01J5/04 ,  G02B19/00 ,  H01L23/26

公开(公告)号：EP3313778A1

公开(公告)日：2018-05-02

申请号：EP16720628.3

申请日：2016-04-20

Applicant: Raytheon Company

Inventor： DIEP, Buu Q. ,  KENNEDY, Adam M. ,  KOCIAN, Thomas Allan ,  LAMB, Mark

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81B7/0041 ,  B81B2201/0207 ,  B81B2201/04 ,  B81C1/00269 ,  B81C1/00317 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0145 ,  B81C2203/019

Abstract: A microelectromechanical systems (MEMS) package includes a substrate extending between a first pair of outer edges to define a length and a second pair of outer edges to define a width. A seal ring assembly is disposed on the substrate and includes at least one seal ring creating a first boundary point adjacent to at least one MEMS device and a second boundary point adjacent at least one of the outer edges. The package further includes a window lid on the seal ring assembly to define a seal gap containing the at least one MEMS device. The seal ring assembly anchors the window lid to the substrate at the second boundary point such that deflection of the window lid into the seal gap is reduced.

公开(公告)号：EP2915190B1

公开(公告)日：2018-03-07

申请号：EP13850327.1

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.