OSCILLATOR SYNCHRONIZING SYSTEM WITH DC CONTROL OF FREE-RUNNING FREQUENCY

    公开(公告)号:CA1196067A

    公开(公告)日:1985-10-29

    申请号:CA427769

    申请日:1983-05-09

    Applicant: RCA CORP

    Abstract: Color reference oscillator comprises a non-inverting amplifier, with positive feedback via a crystal filter linking its output and input. A quadrature phase shift network, coupled to the filter output, delivers phase shifted signals to a pair of independently controlled amplifiers. One of the controlled amplifiers is responsive to control voltage outputs of a burst-responsive phase detector so as to inject phase shifted signals into the oscillator loop, as and when required, to effect synchronization of oscillator with burst component of incoming color television signal. The second of the controlled amplifiers is responsive to a reference DC voltage and to a manually adjustable DC control voltage, and develops a phase shifted signal output, of a magnitude and polarity dependent upon the magnitude and sense of the difference, if any, between the respective DC voltages, for combination with the non-inverting amplifier's output. Variation of the manually adjustable control voltage provides an adjustment of the free-running frequency of the oscillator.

    TRANSLATING CIRCUIT FOR TELEVISION RECEIVER ON-SCREEN GRAPHICS DISPLAY SIGNALS

    公开(公告)号:CA1188405A

    公开(公告)日:1985-06-04

    申请号:CA415303

    申请日:1982-11-10

    Applicant: RCA CORP

    Abstract: A DC coupled signal translating circuit for supplying auxiliary graphics information switching signals to a video signal processor. The switching signal comprises plural switching levels including a quiescent level. The translating circuit includes first and second complementary conductivity input transistors with interconnected emitter signal inputs for receiving switching currents representative of the graphics switching signals via a conductor which undesirably exhibits a parasitic capacitance. The transistors are biased to conduct a nominal quiescent current and develop collector output currents which are proportional to the input switching currents, and which are respectively coupled via current repeating networks to control inputs of the video processor. Switching delays attributable to the parasitic capacitances of the input coupling conductor are significantly reduced due to the emitter voltage clamping action of the input transistors for all conditions of the input switching signals.

    KEYED DC STABILIZATION SYSTEM WITH PROTECTION FROM ERROR INTRODUCTION DURING VERTICAL SYNC INTERVAL

    公开(公告)号:CA1219947A

    公开(公告)日:1987-03-31

    申请号:CA469923

    申请日:1984-12-12

    Applicant: RCA CORP

    Abstract: DC stabilization system for a color TV receiver includes three control loops, each including a keyed comparator for comparing a respectively different one of a set of blue, green and red color signals with a common reference voltage during keying periods determined by line rate keying of "backporch" timing pulses. The output of the keyed comparator responding to the blue signal adjusts the DC level of a luminance signal component used in color signal formation. The output of the keyed comparator responding to the red signal adjusts the DC level of an I color-difference signal component used for color signal formation. The output of the keyed comparator responding to the green signal adjusts the DC level of a Q color-difference signal used for color signal formation. The line rate keying pulse source is subject to field-rate blanking to preclude comparator keying during significant portion of received signal's vertical sync interval.

    TRI-LEVEL SANDCASTLE PULSE DECODER

    公开(公告)号:CA1219339A

    公开(公告)日:1987-03-17

    申请号:CA469208

    申请日:1984-12-03

    Applicant: RCA CORP

    Abstract: RCA 76,343 Trilevel sandcastle pulse decoder includes a trio of voltage comparison means for comparing incoming sandcastle pulses with reference potentials of respectively different levels. One of the voltage comparison means, which is subject to change in operating state in response to appearance of a given level of the sandcastle pulse, is precluded from operating state change in response to the appearance of the next higher level of the sandcastle pulse by control circuitry responsive to the output of a second of the voltage comparison means. One of the decoder outputs is developed by logic circuitry responsive to outputs of two of the comparison means.

    FREQUENCY SELECTIVE DC COUPLED VIDEO SIGNAL CONTROL SYSTEM INSENSITIVE TO VIDEO SIGNAL DC COMPONENTS

    公开(公告)号:CA1185355A

    公开(公告)日:1985-04-09

    申请号:CA413038

    申请日:1982-10-07

    Applicant: RCA CORP

    Abstract: A DC coupled system for automatically controlling the high frequency peaking content of a video signal is disclosed. The system includes a DC coupled control path comprising a peak detector for developing a control voltage representative of the high frequency content of the video signal exclusive of video signal DC components. The detector is preceded in the control path by a frequency selective network comprising an amplifier and a filter for shaping the frequency response of the control path such that high frequency video signal components exclusive of DC video signal components are passed to the peak detector. The frequency selective network comprises the cascode combination of a video signal amplifier transistor and a current source transistor which provides quiescent operating currents for the amplifier transistor. The filter is coupled to the junction of the amplifier and current source transistors, and includes a DC blocking network coupled between the junction and a point of reference potential.

    CLAMPING ARRANGEMENT FOR A VIDEO SIGNAL PEAKING SYSTEM

    公开(公告)号:CA1180106A

    公开(公告)日:1984-12-27

    申请号:CA411580

    申请日:1982-09-16

    Applicant: RCA CORP

    Abstract: RCA 77,259 In a video signal processing system, an input capacitor AC couples video signals to a DC coupled video signal path, and to a DC coupled peaking signal path for generating a peaking component which is combined with video signals from the video path to develop a peaked video signal. A feedback control voltage for controlling the DC level of the video signal is stored by the input coupling capacitor, and is DC coupled to both the video path and the peaking path in a manner to reduce the likelihood of a DC offset error when the video signal and peaking component are combined. In an embodiment, the control voltage is coupled to the storage capacitor via a delay line included in the video path and which is coupled across the differential inputs of a differential amplifier with which the delay line coacts to generate the peaking component.

    AMPLIFIER INCORPORATING GAIN DISTRIBUTION CONTROL FOR CASCADED AMPLIFYING STAGES

    公开(公告)号:CA1192969A

    公开(公告)日:1985-09-03

    申请号:CA422929

    申请日:1983-03-04

    Applicant: RCA CORP

    Abstract: A pair of differential amplifier stages are connected in cascade to form a multistage amplifier for signal amplification purposes. The base-emitter paths of current source transistors which establish the operating currents for the respective stages are connected in series across a common source of forward bias voltage. The collector-emitter path of an additional transistor is shunted across the base-emitter path of one of the current source transistors. As biasing of the additional transistor is varied, the distribution of gain between the respective cascaded stages is altered substantially without disturbance of the overall gain of the multistage amplifier.

    CONTROLLED OUTPUT COMPOSITE KEYING SIGNAL GENERATOR FOR A TELEVISION RECEIVER

    公开(公告)号:CA1159948A

    公开(公告)日:1984-01-03

    申请号:CA368421

    申请日:1981-01-13

    Applicant: RCA CORP

    Abstract: RCA 73,113 A circuit for generating a composite keying signal comprises a burst gate circuit and a voltage translating network in a color television receiver also including keyed signal processing circuits and means for deriving horizontal and vertical blanking signals and a horizontal sync signal from a composite color television signal containing a color burst component. The burst gate circuit responds to the horizontal sync signal to develop a burst gate pulse encompassing the burst interval. A voltage level developed by the translating network in response to the horizontal and vertical blanking signals is combined with the burst gate pulse to produce a composite keying signal. The composite keying signal comprises a first pulse component of a desired level as determined by the translating network and occurring during the blanking intervals, and a second pulse component as provided from the burst gate circuit, superimposed on the first pulse and encompassing the burst interval. Means are also included for inhibiting the output of the keying signal generator during picture intervals of the television signal, to prevent false keying of the keyed circuits in response to keying signals generated by the keying signal generator in the presence of spurious input signals occurring during picture intervals.

    AUTOMATIC KINESCOPE BEAM CURRENT LIMITER WITH SEQUENTIAL CONTROL MODES

    公开(公告)号:CA1156375A

    公开(公告)日:1983-11-01

    申请号:CA366743

    申请日:1980-12-12

    Applicant: RCA CORP

    Abstract: RCA 73,402 An automatic kinescope beam current limiter for a television receiver comprises a source of signal representative of kinescope beam current conduction, a first transistor responsive to the representative signal over first, second and third ranges of excessive beam currents above a threshold level, and a second transistor. A first control signal derived from the first transistor modifies the video signal peak-to-peak amplitude (contrast level) when beam currents above the threshold level occur. The output of the first transistor is selectively coupled to an input of the second transistor when beam currents beyond the first range occur. A second control signal derived from the second transistor modifies the video signal D.C. component (brightness level) to limit beam currents beyond the first range, whereby both the peak amplitude and D.C. components are modified over the second range. The first control signal is clamped to a fixed level in response to beam currents beyond the second range, whereby the video signal D.C. component is modified alone to limit beam currents over the third range.

    COLOR-DIFFERENCE SIGNAL PROCESSING CIRCUITS

    公开(公告)号:CA1153105A

    公开(公告)日:1983-08-30

    申请号:CA371850

    申请日:1981-02-26

    Applicant: RCA CORP

    Abstract: RCA 74,396 A first resistive current path is DC connected between respective output terminals of push-pull color demodulator. A second resistive current path is DC connected between respective output terminals of a second push-pull color demodulator. An output color-difference signal is formed by a differential amplifier having one input DC connected to an asymmetrically positioned point in first resistive current path, and a second input DC connected to an asymmetrically positioned point in second resistive current path. Output color-difference signal corresponds to a combination of the demodulated signals, with a polarity relationship and magnitude ratio determined by the asymmetry of positioning of the takeoff points in the respective current paths. Output quiescent voltage is independent of the asymmetry of positioning of the D takeoff points.

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