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    A linear surface memory to spatial tiling algorithm/mechanism
    5.
    发明专利
    A linear surface memory to spatial tiling algorithm/mechanism 未知

    公开(公告)号：GB2374782A

    公开(公告)日：2002-10-23

    申请号：GB0216638

    申请日：1999-04-01

    Applicant: REAL 3 D INC

    Inventor： HARTOG SCOTT ,  MANTOR MICHAEL ,  CAREY JOHN AUSTIN ,  PIAZZA THOMAS A ,  TAYLOR RALPH CLAYTON ,  RADECKI MATTHEW

    IPC: G06F12/02 ,  G06T1/60

    Abstract: A computer graphics system and a method of configuring data in a memory unit of a computer graphics system. Generally, the data is configured such that the number of memory page breaks is reduced when data is accessed from the memory for image computation. For example, when the memory is used to store pixel values, each page of the memory is comprised of pixel values for a rectangular or tile array of pixels. This increases the spatial coherence between the pixel values and the pixels of the polygons that are rasterized when the system renders an image. Preferably, a translation algorithm is provided to allow standard operating systems and software applications to work with the tiled configuration of the pixel values in the memory. This algorithm translates the scalar memory address initially provided by the operating system or the software application, and translates that first scalar memory address to a second scalar memory address that will properly access the value for the pixel conventionally associated with the first scalar memory address.

    A linear surface memory to spatial tiling algorithm/mechanism
    6.
    发明专利
    A linear surface memory to spatial tiling algorithm/mechanism 未知

    公开(公告)号：GB2374781A

    公开(公告)日：2002-10-23

    申请号：GB0216637

    申请日：1999-04-01

    Applicant: REAL 3 D INC

    Inventor： HARTOG SCOTT ,  MANTOR MICHAEL ,  CAREY JOHN AUSTIN ,  PIAZZA THOMAS A ,  TAYLOR RALPH CLAYTON ,  RADECKI MATTHEW

    IPC: G06F12/02 ,  G06T1/60

    Abstract: A computer graphics system and a method of configuring data in a memory unit of a computer graphics system. Generally, the data is configured such that the number of memory page breaks is reduced when data is accessed from the memory for image computation. For example, when the memory is used to store pixel values, each page of the memory is comprised of pixel values for a rectangular or tile array of pixels. This increases the spatial coherence between the pixel values and the pixels of the polygons that are rasterized when the system renders an image. Preferably, a translation algorithm is provided to allow standard operating systems and software applications to work with the tiled configuration of the pixel values in the memory. This algorithm translates the scalar memory address initially provided by the operating system or the software application, and translates that first scalar memory address to a second scalar memory address that will properly access the value for the pixel conventionally associated with the first scalar memory address.

    A linear surface memory to spatial tiling algorithm/mechanism
    7.
    发明专利
    A linear surface memory to spatial tiling algorithm/mechanism 未知

    公开(公告)号：GB2374780A

    公开(公告)日：2002-10-23

    申请号：GB0216636

    申请日：1999-04-01

    Applicant: REAL 3 D INC

    Inventor： HARTOG SCOTT ,  MANTOR MICHAEL ,  CAREY JOHN AUSTIN ,  PIAZZA THOMAS A ,  TAYLOR RALPH CLAYTON ,  RADECKI MATTHEW

    IPC: G06F12/02 ,  G06T1/60

    Abstract: A computer graphics system and a method of configuring data in a memory unit of a computer graphics system. Generally, the data is configured such that the number of memory page breaks is reduced when data is accessed from the memory for image computation. For example, when the memory is used to store pixel values, each page of the memory is comprised of pixel values for a rectangular or tile array of pixels. This increases the spatial coherence between the pixel values and the pixels of the polygons that are rasterized when the system renders an image. Preferably, a translation algorithm is provided to allow standard operating systems and software applications to work with the tiled configuration of the pixel values in the memory. This algorithm translates the scalar memory address initially provided by the operating system or the software application, and translates that first scalar memory address to a second scalar memory address that will properly access the value for the pixel conventionally associated with the first scalar memory address.

    BEHAVIORAL MODEL BASED MULTI-THREADED ARCHITECTURE
    8.
    发明申请
    BEHAVIORAL MODEL BASED MULTI-THREADED ARCHITECTURE 审中-公开
    基于行为模型的多层建筑

    公开(公告)号：WO2005066768A3

    公开(公告)日：2007-02-22

    申请号：PCT/US2004043395

    申请日：2004-12-23

    Applicant: INTEL CORP ,  JIANG HONG ,  PIAZZA THOMAS A

    Inventor： JIANG HONG ,  PIAZZA THOMAS A

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48

    CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/4843

    Abstract: Multiple parallel passive threads of instructions coordinate access to shared resources using "active" and "proactive" semaphores. The active semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state. A proactive semaphore operates in a similar manner except that the semaphore is configured by the thread dispatcher before or after the thread is dispatched to the execution circuitry for execution.

    Abstract translation: 指令的多个并行被动线程使用“主动”和“主动”信号量协调对共享资源的访问。 主动信号量将消息发送到执行和/或控制电路，以使线程的状态发生变化。 线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。 与依赖关系对应的线程状态变量用于指示线程处于非活动模式。 当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。 响应于清除的依赖变量，线程处于活动状态。 处于活动状态的线程可执行。 主动信号量以类似的方式运行，除了信号量由线程分派器在线程发送到执行电路执行之前或之后配置。

    METHOD AND APPARATUS FOR ARBITRATION IN A UNIFIED MEMORY ARCHITECTURE
    10.
    发明申请
    METHOD AND APPARATUS FOR ARBITRATION IN A UNIFIED MEMORY ARCHITECTURE 审中-公开
    在统一的存储器架构中进行仲裁的方法和装置

    公开(公告)号：WO0041083A3

    公开(公告)日：2002-05-16

    申请号：PCT/US9930719

    申请日：1999-12-21

    Applicant: INTEL CORP ,  CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

    Inventor： CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362

    CPC classification number: G06F13/18

    Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.

    Abstract translation: 根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控​​制器的计算机系统。 存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。 计算机系统还包括耦合到仲裁单元的第一设备和第二设备。 根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。 此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

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