公开(公告)号：US20040183122A1

公开(公告)日：2004-09-23

申请号：US10766188

申请日：2004-01-29

Applicant: Renesas Technology Corp.

Inventor： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC: H01L029/788

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

Abstract translation: 一种非易失性半导体存储器件，由具有栅极绝缘膜和选择栅电极的选择MOS晶体管构成，以及具有电容绝缘膜的存储MOS晶体管，该MOS晶体管具有下部势垒膜，电荷俘获膜和 上电势势垒膜，以及存储栅电极。 电荷捕获膜由氧氮化硅膜形成，并且省略上电势阻挡膜或将其厚度限制在1nm以下，以防止由氮氧化硅膜引起的Gm劣化，从而降低擦除栅极电压。 电荷捕获膜由形成在氧氮化硅膜上或下面的主电荷俘获膜和氮化硅膜形成，以形成仅对孔有效的势垒。 并且，采用热孔擦除方法来降低擦除电压。

公开(公告)号：US20040155234A1

公开(公告)日：2004-08-12

申请号：US10743783

申请日：2003-12-24

Applicant: Renesas Technology Corp.

Inventor： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

IPC: G11C011/34

CPC classification number: G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

Abstract translation: 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅电极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。