公开(公告)号：US20040104425A1

公开(公告)日：2004-06-03

申请号：US10721874

申请日：2003-11-26

Applicant: Renesas Technology Corp.

Inventor： Takashi Kobayashi ,  Toshiyuki Mine

IPC: H01L021/82 ,  H01L029/76

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/792

Abstract: This invention is intended to improve reliability of a nonvolatile semiconductor memory device and reduces a memory cell size of the nonvolatile semiconductor memory device. A memory cell which includes source/drain diffusion layers in a p-type well formed in a silicon substrate, silicon nitride dots which are located between silicon oxide films and into which charges are injected, a control gate 212, and assist gates is formed. Programming is conducted to the memory cell by injecting electrons into the drain-side silicon nitride dots or the source-side silicon nitride dots. Since silicon nitride serving as a charge injected section is in the form of dots, it is possible to suppress movement of the charges in a channel direction, to prevent the charges on a source end portion and those on a drain end portion from being mixed together, and to improve charge holding characteristic of the memory cell. Even in the case where a gate length is shortened, the charge holding characteristic can be secured.

Abstract translation: 本发明旨在提高非易失性半导体存储器件的可靠性并减小非易失性半导体存储器件的存储单元尺寸。 一种存储单元，其包括在硅衬底中形成的p型阱中的源极/漏极扩散层，形成位于氧化硅膜之间并且其中注入电荷的氮化硅点，控制栅极212和辅助栅极。 通过向漏极侧氮化硅点或源极氮化硅点注入电子，对存储单元进行编程。 由于用作电荷注入部分的氮化硅是点的形式，可以抑制电荷在沟道方向上的移动，以防止源端部分上的电荷和排出端部上的电荷混合在一起 并且改善存储单元的电荷保持特性。 即使在栅极长度缩短的情况下，也可以确保电荷保持特性。

公开(公告)号：US20040183122A1

公开(公告)日：2004-09-23

申请号：US10766188

申请日：2004-01-29

Applicant: Renesas Technology Corp.

Inventor： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC: H01L029/788

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

Abstract translation: 一种非易失性半导体存储器件，由具有栅极绝缘膜和选择栅电极的选择MOS晶体管构成，以及具有电容绝缘膜的存储MOS晶体管，该MOS晶体管具有下部势垒膜，电荷俘获膜和 上电势势垒膜，以及存储栅电极。 电荷捕获膜由氧氮化硅膜形成，并且省略上电势阻挡膜或将其厚度限制在1nm以下，以防止由氮氧化硅膜引起的Gm劣化，从而降低擦除栅极电压。 电荷捕获膜由形成在氧氮化硅膜上或下面的主电荷俘获膜和氮化硅膜形成，以形成仅对孔有效的势垒。 并且，采用热孔擦除方法来降低擦除电压。

公开(公告)号：US20040198019A1

公开(公告)日：2004-10-07

申请号：US10814627

申请日：2004-04-01

Applicant: Renesas Technology Corp.

Inventor： Kan Yasui ,  Toshiyuki Mine ,  Yasushi Goto ,  Natsuki Yokoyama

IPC: H01L021/76

CPC classification number: H01L21/76224 ,  Y10S438/907

Abstract: In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.

Abstract translation: 为了实现根据本发明的隔离沟槽形成方法，其中可以容易地控制氮化硅膜衬垫的结构并且允许器件特征长度的减小和在隔离沟槽中发生的应力的减小， 氮化硅膜衬垫首先沉积在形成在硅衬底上的沟槽的内壁上。 用于填充沟槽内部的第一嵌入式绝缘体膜的上表面向下凹入以暴露氮化硅膜衬垫的上端部分。 接下来，将氮化硅膜衬垫的露出部分转换成诸如氧化硅膜的非氮化硅型绝缘膜。 然后将第二嵌入式绝缘膜沉积在第一嵌入式绝缘膜的上部上，然后将沉积的表面平坦化。