公开(公告)号：US20040183122A1

公开(公告)日：2004-09-23

申请号：US10766188

申请日：2004-01-29

Applicant: Renesas Technology Corp.

Inventor： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC: H01L029/788

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

Abstract translation: 一种非易失性半导体存储器件，由具有栅极绝缘膜和选择栅电极的选择MOS晶体管构成，以及具有电容绝缘膜的存储MOS晶体管，该MOS晶体管具有下部势垒膜，电荷俘获膜和 上电势势垒膜，以及存储栅电极。 电荷捕获膜由氧氮化硅膜形成，并且省略上电势阻挡膜或将其厚度限制在1nm以下，以防止由氮氧化硅膜引起的Gm劣化，从而降低擦除栅极电压。 电荷捕获膜由形成在氧氮化硅膜上或下面的主电荷俘获膜和氮化硅膜形成，以形成仅对孔有效的势垒。 并且，采用热孔擦除方法来降低擦除电压。